公开(公告)号：US10164524B1

公开(公告)日：2018-12-25

申请号：US15169505

申请日：2016-05-31

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Tara Vishin

IPC: H02M3/155 ,  G11C7/20 ,  G06F1/32 ,  G11C11/4074

Abstract: Embodiments relate to circuits, electronic design assistance (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on different supply voltages. In one embodiment, a programmable level translator device is implemented using an NMOS transistor pair and a PMOS cross quad. The switching characteristics are modified with the use of a charge pump connected to the gate terminals of two of the PMOS transistors within the PMOS cross quad. Transmission gates are also employed to engage and disengage the charge pump based on a control switch. In various embodiments, the level translator device works with a number of memory devices operating over a wide range of power supply voltages.

公开(公告)号：US09997214B1

公开(公告)日：2018-06-12

申请号：US15637711

申请日：2017-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Tara Vishin

IPC: G11C7/00 ,  G11C7/10 ,  G11C14/00 ,  G11C5/14 ,  G11C11/40 ,  H03K19/173 ,  H03K19/00 ,  H03K19/0185

CPC classification number: G11C7/1057 ,  G11C5/145 ,  G11C5/147 ,  G11C7/1069 ,  G11C11/40 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4096 ,  G11C14/0009 ,  G11C2207/105 ,  H03K19/00 ,  H03K19/0005 ,  H03K19/0185 ,  H03K19/018521 ,  H03K19/173 ,  H03K19/1733

Abstract: Disclosed is an architecture for an output driver that does not employ level shifters in the high speed data path. Since the proposed architecture is free from level shifters in the high speed data path, it provides better performance across PVT corners. The disclosed output driver usages a hybrid pullup driver which makes it compatible for the wide range of DRAM supply range. This approach allows for significant savings for electronic design area and dynamic power.

公开(公告)号：US09754646B1

公开(公告)日：2017-09-05

申请号：US15342974

申请日：2016-11-03

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Tara Vishin ,  Sachin Ramesh Gugwad ,  Thomas Evan Wilson

IPC: G11C7/12 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093

Abstract: Embodiments relate to circuits, electronic design automation (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on a different supply voltage using low power and high data rates while avoiding voltage over-stress of thin-oxide transistors. In an embodiment, channels of a thin-oxide PMOS transistor, a thick-oxide PMOS transistor, a thick-oxide NMOS transistor, and a thin-oxide NMOS transistor are coupled in order from a memory device voltage supply rail to a low voltage supply rail. Gates of the thin-oxide PMOS transistor and the thick-oxide NMOS transistor are coupled with an output of a flying capacitor circuit that level-shifts an input signal by a difference between the memory device supply and core supply voltages, while gates of the thick-oxide PMOS transistor and the thin-oxide NMOS transistor receive the input signal via a buffer.