公开(公告)号：US09494557B2

公开(公告)日：2016-11-15

申请号：US14001963

申请日：2012-04-05

申请人： Cagri A. Savran ,  Chung-Li Chang ,  Philip S. Low

发明人： Cagri A. Savran ,  Chung-Li Chang ,  Philip S. Low

IPC分类号： G01N33/553 ,  G01N27/74 ,  G01N33/543 ,  B01L3/00 ,  G01N33/574 ,  G01N1/40

CPC分类号： B01L3/502761 ,  B01L3/50273 ,  B01L2200/0652 ,  B01L2200/0668 ,  B01L2300/0877 ,  B01L2400/043 ,  G01N27/745 ,  G01N33/54326 ,  G01N33/574 ,  G01N33/57434 ,  G01N33/57492 ,  G01N2001/4016

摘要： A microfluidic detection system for micrometer-sized entities, such as biological cells, includes a detector component incorporating a plate with a plurality of opening, the plate separating two chambers, one in communication with a fluid source containing target cells bound to magnetic beads. The openings are sized to always permit passage of the magnetic beads therethrough into a lower one of the chambers and are further sized to always prevent passage of the target cells from the upper one of the chambers. The detector component further includes a magnet positioned to pull unbound magnetic beads through the openings and to capture target cells bound to magnetic beads on the surface of the plate. The microfluidic detection system includes a pump flowing the fluid through the detector component at high flow rates of milliliters per minute for high throughput detection of target cells.

摘要翻译： 用于微米尺寸实体（例如生物细胞）的微流体检测系统包括结合有多个开口的板的检测器部件，该板分离两个室，一个与包含与磁珠结合的靶细胞的流体源连通。 这些开口的尺寸设置成总是允许磁珠通过其进入下部的一个室，并且进一步的尺寸设计成总是防止靶细胞从上部的一个室中通过。 检测器部件还包括磁铁，该磁体定位成将未结合的磁珠拉过开口并捕获与板表面上的磁珠结合的靶细胞。 微流体检测系统包括泵以高分子量/分钟的速度流过检测器部件，用于目标细胞的高通量检测。

公开(公告)号：US06465836B2

公开(公告)日：2002-10-15

申请号：US09821199

申请日：2001-03-29

申请人： Chrong Jung Lin ,  Sheng-Wei Tsao ,  Di-Son Kuo ,  Jack Yeh ,  Wen-Ting Chu ,  Chung-Li Chang ,  Chia-Ta Hsieh

发明人： Chrong Jung Lin ,  Sheng-Wei Tsao ,  Di-Son Kuo ,  Jack Yeh ,  Wen-Ting Chu ,  Chung-Li Chang ,  Chia-Ta Hsieh

IPC分类号： H01L29788

CPC分类号： H01L29/7887 ,  H01L29/42336

摘要： Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field effect transistor (FET) device. Similarly, there is also formed within the split gate field effect transistor a floating gate electrode within the trench and covering within the trench a lower sub-portion of the channel region. Finally, the floating gate electrode in turn has formed vertically and horizontally overlapping thereover within the trench a control gate electrode which covers an upper sub-portion of the channel. The split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.

摘要翻译： 在分裂栅场效应晶体管（FET）器件和用于制造分离栅场效应晶体管（FET）器件的方法中，在半导体衬底内形成沟槽，其沟槽内的沟槽区域完全包含在分离栅极场内 效应晶体管（FET）器件。 类似地，在分裂栅极场效应晶体管内还形成有沟槽内的浮置栅电极，并且在沟槽内覆盖沟道区的下部子部分。 最后，浮栅电极依次形成在沟槽内垂直和水平重叠的覆盖通道的上部子部分的控制栅电极。 分离栅场效应晶体管（FET）器件制造具有增强的面密度和增强的性能。

公开(公告)号：US06420233B1

公开(公告)日：2002-07-16

申请号：US09766860

申请日：2001-01-19

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chung-Li Chang ,  Wen-Ting Chu ,  Chrong-Jung Lin

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chung-Li Chang ,  Wen-Ting Chu ,  Chrong-Jung Lin

IPC分类号： H01L29336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is employed a doped polysilicon floating gate electrode having an central annular portion having a higher dopant concentration than a peripheral annular portion of the doped polysilicon floating gate electrode. The higher dopant concentration within the central annular portion of the doped polysilicon floating gate electrode provides enhanced programming speed properties of the split gate field effect transistor (FET) device. The lower dopant concentration within the peripheral annular portion of the doped polysilicon floating gate electrode provides enhanced erasing speed properties within the split gate field effect transistor (FET) device under certain circumstances of fabrication of the split gate field effect transistor (FET) device.

摘要翻译： 在分裂栅场效应晶体管（FET）器件和用于制造分离栅场效应晶体管（FET）器件的方法中，采用掺杂多晶硅浮栅，其具有中间环状部分，其掺杂浓度高于周边环形 掺杂多晶硅浮栅电极的一部分。 掺杂多晶硅浮置栅电极的中心环形部分内的较高掺杂剂浓度提供了分裂栅极场效应晶体管（FET）器件的增强的编程速度特性。 在掺杂多晶硅浮置栅电极的外围环形部分内的较低掺杂剂浓度在分裂栅极场效应晶体管（FET）器件的制造的某些情况下在分裂栅极场效应晶体管（FET）器件内提供增强的擦除速度特性。

公开(公告)号：US06297099B1

公开(公告)日：2001-10-02

申请号：US09765045

申请日：2001-01-19

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jack Yeh ,  Chrong Jung Lin ,  Wen-Ting Chu ,  Chung-Li Chang

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jack Yeh ,  Chrong Jung Lin ,  Wen-Ting Chu ,  Chung-Li Chang

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  Y10S438/981

摘要： A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion. A polysilicon layer is formed over the interpoly oxide layer. The structure is patterned to form a floating gate/word line device.

摘要翻译： 一种制造浮栅/字线装置的方法，包括以下步骤。 提供半导体结构。 在半导体结构上方形成浮栅部分。 浮动门部分具有侧壁和顶面。 多晶氧化物部分形成在浮动栅极的顶表面上。 在半导体结构，多晶氧化物部分和多晶氧化物部分之上形成多层氧化物层。 所述多晶硅氧化物层具有初始厚度，并且包括：与所述浮动栅极部分相邻的所述半导体结构的至少一部分上的字线区域部分; 浮动部分侧壁上的侧壁区域部分; 以及多个氧化物部分上方的顶部。 互折层氧化物层的顶部的初始厚度减小到第二厚度，而不会减小多晶氧化物字线区域部分的初始厚度或多余氧化物侧壁区域部分的明显部分。 在多晶硅层上形成多晶硅层。 将结构图案化以形成浮动栅/字线装置。