公开(公告)号：US06255128B1

公开(公告)日：2001-07-03

申请号：US09130240

申请日：1998-08-06

申请人： Carlos M. Chacon ,  Pradip K. Roy

发明人： Carlos M. Chacon ,  Pradip K. Roy

IPC分类号： B01R3126

CPC分类号： G01N27/002 ,  H01L22/12

摘要： The present invention provides a non-contact method for determining whether a contaminant is present in a semiconductor wafer having a substrate/dielectric interface formed thereon. in one advantageous embodiment, the method comprises field inducing a junction in equilibrium inversion in the semiconductor wafer device. A conventional corona source may be used to induce the junction to equilibrium inversion. This particular embodiment further includes forming a contaminant junction near the substrate/dielectric interface when the contaminant is present in the semiconductor wafer by adding charge and pulsing the junction out of equilibrium. A surface voltage measurement, which may be taken with a Kelvin probe, is obtained by measuring a change in a surface voltage as a function of time. The method further includes determining whether the contaminant is present in the semiconductor wafer from the change in the surface voltage. When the contaminant is present in the device, the change in the surface voltage is negligible. This negligible change is in stark contrast to the change in surface voltage that occurs in a non-contaminated device. The data obtained from these surface voltages can be plotted with conventional devices to yield the change in surface voltage with respect to time.

摘要翻译： 本发明提供了一种用于确定在其上形成有衬底/电介质界面的半导体晶片中是否存在污染物的非接触方法。 在一个有利的实施例中，该方法包括在半导体晶片装置中的场平衡反转中的场感应。 传统的电晕源可以用来诱导结到平衡反转。 该特定实施例还包括当通过添加电荷并将结合脉冲到平衡之外，当污染物存在于半导体晶片中时，在衬底/电介质界面附近形成污染物结。 通过测量作为时间的函数的表面电压的变化可获得可以用开尔文探针进行的表面电压测量。 该方法还包括根据表面电压的变化确定污染物是否存在于半导体晶片中。 当设备中存在污染物时，表面电压的变化可以忽略不计。 这个微不足道的变化与在非污染设备中发生的表面电压的变化形成鲜明的对比。 从这些表面电压获得的数据可以用常规装置绘制，以产生相对于时间的表面电压的变化。

公开(公告)号：US06548422B1

公开(公告)日：2003-04-15

申请号：US09966779

申请日：2001-09-27

申请人： Pradip K. Roy ,  David C. Brady ,  Carlos M. Chacon

发明人： Pradip K. Roy ,  David C. Brady ,  Carlos M. Chacon

IPC分类号： H01L2348

CPC分类号： H01L21/28185 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor gate dielectric structure includes an oxide layer formed on a substrate, a superjacent nitride layer and a transition layer interposed therebetween. The presence of the transition layer alleviates stress between the nitride and oxide layers and minimizes any charge trapping sites between the nitride and oxide layers. The transition layer includes both nitrogen and oxygen as components. The method for forming the structure includes forming the transition layer using a remote nitridation reactor at a sufficiently low temperature such that virtually no nitrogen reaches the interface formed between the oxide layer and the substrate. The oxide layer/substrate interface is relatively pristine and defect-free. In an exemplary embodiment, the oxide layer may be a graded structure formed using two distinct processing operations, a first operation at a relatively low temperature and a final operation at a temperature above the viscoelastic temperature of the oxide film.

摘要翻译： 晶体管栅极电介质结构包括形成在衬底上的氧化物层，超临界氮化物层和介于其间的过渡层。 过渡层的存在减轻氮化物和氧化物层之间的应力，并使氮化物和氧化物层之间的任何电荷俘获位置最小化。 过渡层包括氮和氧作为组分。 形成结构的方法包括在足够低的温度下使用远程氮化反应器形成过渡层，使得实际上没有氮到达氧化物层和衬底之间形成的界面。 氧化物层/衬底界面相对原始且无缺陷。 在示例性实施例中，氧化物层可以是使用两种不同的加工操作形成的渐变结构，在较低温度下的第一操作和在高于氧化膜的粘弹性温度的温度下的最终操作。

公开(公告)号：US06391668B1

公开(公告)日：2002-05-21

申请号：US09562346

申请日：2000-05-01

申请人： Carlos M. Chacon ,  Sundar S. Chetlur ,  Brian E. Harding ,  Minesh A. Patel ,  Pradip K. Roy

发明人： Carlos M. Chacon ,  Sundar S. Chetlur ,  Brian E. Harding ,  Minesh A. Patel ,  Pradip K. Roy

IPC分类号： H01L2166

CPC分类号： H01L22/14

摘要： The present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface, and determining the trap density as a function of the measured current.

摘要翻译： 本发明提供一种确定半导体衬底/电介质界面的阱密度的方法。 在一个实施例中，该方法包括测量由位于接口附近的陷阱的载流子导致的半导体衬底内的电流，其中测量的电流是位于界面处的陷阱的数量的函数，并且将陷阱密度确定为 测量电流的函数。

公开(公告)号：US06265890B1

公开(公告)日：2001-07-24

申请号：US09383457

申请日：1999-08-26

申请人： Carlos M. Chacon ,  Sailesh Chittipeddi ,  Pradip K. Roy

发明人： Carlos M. Chacon ,  Sailesh Chittipeddi ,  Pradip K. Roy

IPC分类号： G01R3102

CPC分类号： G01R27/2611

摘要： A method and apparatus for in-line, non-contact depletion capacitance measurement of a semiconductor wafer using non-contact voltage measurement and non-contact surface photovoltage response.

摘要翻译： 一种使用非接触电压测量和非接触表面光电压响应的半导体晶片的在线非接触耗尽电容测量的方法和装置。

公开(公告)号：US06207468B1

公开(公告)日：2001-03-27

申请号：US09178317

申请日：1998-10-23

申请人： Carlos M. Chacon ,  Pradip K. Roy

发明人： Carlos M. Chacon ,  Pradip K. Roy

IPC分类号： H01L2166

CPC分类号： H01L22/12

摘要： The present invention provides a method for controlling a process parameter for fabricating a semiconductor wafer. In one embodiment, the method includes forming a test substrate using a given process parameter, determining a flatband voltage of the test substrate, and modifying the given process parameter to cause the flatband voltage to approach zero. The process parameter that is modified to cause the flatband voltage to approach zero may vary. The flatband may be determined by a non-contact method, which uses a kelvin probe to measure the flatband voltage and a corona source to deposit a charge on the test substrate.

摘要翻译： 本发明提供一种用于控制用于制造半导体晶片的工艺参数的方法。 在一个实施例中，该方法包括使用给定的工艺参数形成测试衬底，确定测试衬底的平带电压，以及修改给定的工艺参数以使扁平带电压接近零。 修改以使扁平电压接近零的工艺参数可能会有所不同。 扁平带可以通过使用开尔文探针来测量平带电压的非接触方法来确定，并且电晕源可以在测试基板上沉积电荷。

公开(公告)号：US06664800B2

公开(公告)日：2003-12-16

申请号：US09756965

申请日：2001-01-08

申请人： Carlos M. Chacon ,  Sundar Chetlur ,  Pradip K. Roy

发明人： Carlos M. Chacon ,  Sundar Chetlur ,  Pradip K. Roy

IPC分类号： G01R3100

CPC分类号： G01R31/2648 ,  G01R31/129

摘要： A non-contact method for determining a quality of a semiconductor dielectric. The method includes depositing a charge on a dielectric to achieve a high voltage on the dielectric, measuring a voltage drop of the dielectric as a function of time, and determining a soft breakdown voltage of the dielectric from the voltage drop as a function of time. The amount of charge that is deposited may vary. For example, the charge may be deposited until a voltage that ranges from about 4 megavolts to about 16 megavolts is achieved on the dielectric. The amount of charge may also depend on the thickness of the dielectric. For example, applying a charge as a function of the thickness may include applying 4 megavolts when the thickness is about 1.2 nm or applying 16 megavolts when the thickness is about 5.0 nm.

摘要翻译： 一种用于确定半导体电介质质量的非接触方法。 该方法包括在电介质上沉积电荷以在电介质上实现高电压，测量作为时间的函数的电介质的电压降，以及根据时间从电压降确定电介质的软击穿电压。 存放的电荷量可能会有所不同。 例如，可以在电介质上实现电荷，直到达到约4兆伏特至约16兆伏特的电压。 电荷量也可以取决于电介质的厚度。 例如，作为厚度的函数施加电荷可以包括当厚度为约1.2nm时应用4兆伏，或者当厚度为约5.0nm时施加16兆伏特。

公开(公告)号：US06251697B1

公开(公告)日：2001-06-26

申请号：US09684015

申请日：2000-10-06

申请人： Carlos M. Chacon ,  Pradip K. Roy

发明人： Carlos M. Chacon ,  Pradip K. Roy

IPC分类号： H01L2166

CPC分类号： H01L22/12

摘要： The present invention provides a method for controlling a process parameter for fabricating a semiconductor wafer. In one embodiment, the method includes forming a test substrate using a given process parameter, determining a flatband voltage of the test substrate, and modifying the given process parameter to cause the flatband voltage to approach zero. The process parameter that is modified to cause the flatband voltage to approach zero may vary. The flatband may be determined by a non-contact method, which uses a kelvin probe to measure the flatband voltage and a corona source to deposit a charge on the test substrate.

公开(公告)号：US08932116B2

公开(公告)日：2015-01-13

申请号：US13612135

申请日：2012-09-12

申请人： Manish Deopura ,  Hem M. Vaidya ,  Pradip K. Roy

发明人： Manish Deopura ,  Hem M. Vaidya ,  Pradip K. Roy

IPC分类号： B24B37/26 ,  B24D15/04 ,  B24D18/00 ,  B29C33/42 ,  B29C33/56 ,  B29C33/38 ,  B29C33/40 ,  B29K83/00

CPC分类号： B24B37/26 ,  B24D15/04 ,  B24D18/0009 ,  B29C33/3842 ,  B29C33/405 ,  B29C33/424 ,  B29C33/565 ,  B29K2083/00 ,  B33Y80/00

摘要： Methods for producing in-situ grooves in CMP pads are provided. In general, the methods for producing in-situ grooves comprise the steps of patterning a silicone lining, placing the silicone lining in, or on, a mold, adding CMP pad material to the silicone lining, and allowing the CMP pad to solidify. CMP pads comprising novel groove designs are also described. For example, described here are CMP pads comprising concentric circular grooves and axially curved grooves, reverse logarithmic grooves, overlapping circular grooves, lassajous groves, double spiral grooves, and multiply overlapping axially curved grooves. The CMP pads may be made from polyurethane, and the grooves produced therein may be made by a method from the group consisting of silicone lining, laser writing, water jet cutting, 3-D printing, thermoforming, vacuum forming, micro-contact printing, hot stamping, and mixtures thereof.

摘要翻译： 提供了用于在CMP垫中产生原位凹槽的方法。 通常，用于制造原位槽的方法包括将硅衬里图案化，将硅衬里放置在模具中或模具上，将CMP衬垫材料添加到硅衬里，并允许CMP垫固化的步骤。 还描述了包括新颖凹槽设计的CMP垫。 例如，这里描述的是包括同心圆形槽和轴向弯曲槽，反向对数槽，重叠圆形槽，拉索格，双螺旋槽和多重重叠的轴向曲线槽的CMP垫。 CMP垫可以由聚氨酯制成，并且其中产生的凹槽可以由以下方法制成：由硅胶衬里，激光书写，水射流切割，3-D印刷，热成型，真空成型，微接触印刷， 热冲压及其混合物。

公开(公告)号：US08029849B2

公开(公告)日：2011-10-04

申请号：US10944209

申请日：2004-09-17

申请人： Stephen B. Richey ,  Guoshen Yang ,  Myung Hee Lohman ,  Mary E. Steele ,  Brian M. Reifsteck ,  Pradip K. Roy ,  Sylvia L. Schonauer

发明人： Stephen B. Richey ,  Guoshen Yang ,  Myung Hee Lohman ,  Mary E. Steele ,  Brian M. Reifsteck ,  Pradip K. Roy ,  Sylvia L. Schonauer

IPC分类号： A23G3/54

CPC分类号： A23G3/2015 ,  A23G3/0021 ,  A23G3/0242 ,  A23G3/2023 ,  A23G3/42 ,  A23G3/48 ,  A23G3/54 ,  A23G4/20

摘要： A multi-piece food product (10) comprising a plurality of strands (12A-12K) that are extruded and aggregated to form an aesthetically pleasing food product is provided. A formulation used to make each of the strands (12A-12K) includes a mixture comprising at least 20% sweetener, at least 15% starchy material, and at least 1% fruit by weight based a total dry weight of the mixture to yield a starch-based confectionary food product. One process for forming the multi-piece food product (10) includes extruding a food stream from a slurry, dividing the food stream into three separate food streams (24A, 24B), injecting color, flavor, and ascorbic acid into the food streams (24A, 24B), conveying the food streams (24A, 24B) into a former (26) and extruding the strands (12A-12K) therefrom, forming the strands (12A, 12B) into an aggregate food mass (31), cooling the food mass (31), and cutting the food mass (31) into individual portions.

摘要翻译： 提供了一种多片食品（10），其包括被挤出和聚集以形成美学上令人满意的食品的多根股线（12A-12K）。 用于制备每条链（12A-12K）的制剂包含基于混合物的总干重的包含至少20％甜味剂，至少15％淀粉质材料和至少1重量％果糖的混合物，以产生 淀粉型糖果食品。 用于形成多片食品（10）的一个方法包括从浆料挤出食物流，将食物流分成三个独立的食物流（24A，24B），将颜色，风味剂和抗坏血酸注入食物流中 24A，24B），将食物流（24A，24B）输送到成形器（26）中并从其中挤出股线（12A-12K），将股线（12A，12B）形成为集料食品（31），冷却 食物块（31），并将食物块（31）切割成单独的部分。

公开(公告)号：US20090053976A1

公开(公告)日：2009-02-26

申请号：US11884829

申请日：2006-02-21

申请人： Pradip K. Roy ,  Manish Deopura ,  Sudhanshu Misra

发明人： Pradip K. Roy ,  Manish Deopura ,  Sudhanshu Misra

IPC分类号： B24D18/00 ,  B24D3/00 ,  B24D11/00 ,  B24B7/22

CPC分类号： B24B37/24 ,  B33Y80/00

摘要： The present application relates to polishing pads for chemical mechanical planarization (CMP) of substrates, and methods of fabrication and use thereof. The pads described in this invention are customized to polishing specifications where specifications include (but not limited to) to the material being polished, chip design and architecture, chip density and pattern density, equipment platform and type of slurry used. These pads can be designed with a specialized polymeric nano-structure with a long or short range order which allows for molecular level tuning achieving superior thermo-mechanical characteristics. More particularly, the pads can be designed and fabricated so that there is both uniform and nonuniform spatial distribution of chemical and physical properties within the pads. In addition, these pads can be designed to tune the coefficient of friction by surface engineering, through the addition of solid lubricants, and creating low shear integral pads having multiple layers of polymeric material which form an interface parallel to the polishing surface. The pads can also have controlled porosity, embedded abrasive, novel grooves on the polishing surface, for slurry transport, which are produced in situ, and a transparent region for endpoint detection.

摘要翻译： 本申请涉及用于基板的化学机械平面化（CMP）的抛光垫及其制造和使用方法。 本发明中描述的焊盘定制为抛光规格，其中规格包括（但不限于）被抛光材料，芯片设计和结构，芯片密度和图案密度，设备平台和使用的浆料类型。 这些垫可以设计成具有长或短范围顺序的专门的聚合物纳米结构，其允许分子水平调节实现优异的热机械特性。 更具体地，可以设计和制造焊盘，使得焊盘内的化学和物理性质均匀和不均匀的空间分布。 此外，这些垫可以被设计成通过表面工程，通过添加固体润滑剂来调节摩擦系数，并且产生具有形成与抛光表面平行的界面的多层聚合材料的低剪切整体垫。 焊盘还可以具有受控的孔隙率，嵌入式研磨剂，抛光表面上的新型凹槽，用于原位生产的浆料输送，以及用于端点检测的透明区域。