公开(公告)号：US06548422B1

公开(公告)日：2003-04-15

申请号：US09966779

申请日：2001-09-27

申请人： Pradip K. Roy ,  David C. Brady ,  Carlos M. Chacon

发明人： Pradip K. Roy ,  David C. Brady ,  Carlos M. Chacon

IPC分类号： H01L2348

CPC分类号： H01L21/28185 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor gate dielectric structure includes an oxide layer formed on a substrate, a superjacent nitride layer and a transition layer interposed therebetween. The presence of the transition layer alleviates stress between the nitride and oxide layers and minimizes any charge trapping sites between the nitride and oxide layers. The transition layer includes both nitrogen and oxygen as components. The method for forming the structure includes forming the transition layer using a remote nitridation reactor at a sufficiently low temperature such that virtually no nitrogen reaches the interface formed between the oxide layer and the substrate. The oxide layer/substrate interface is relatively pristine and defect-free. In an exemplary embodiment, the oxide layer may be a graded structure formed using two distinct processing operations, a first operation at a relatively low temperature and a final operation at a temperature above the viscoelastic temperature of the oxide film.

摘要翻译： 晶体管栅极电介质结构包括形成在衬底上的氧化物层，超临界氮化物层和介于其间的过渡层。 过渡层的存在减轻氮化物和氧化物层之间的应力，并使氮化物和氧化物层之间的任何电荷俘获位置最小化。 过渡层包括氮和氧作为组分。 形成结构的方法包括在足够低的温度下使用远程氮化反应器形成过渡层，使得实际上没有氮到达氧化物层和衬底之间形成的界面。 氧化物层/衬底界面相对原始且无缺陷。 在示例性实施例中，氧化物层可以是使用两种不同的加工操作形成的渐变结构，在较低温度下的第一操作和在高于氧化膜的粘弹性温度的温度下的最终操作。

公开(公告)号：US6090686A

公开(公告)日：2000-07-18

申请号：US878242

申请日：1997-06-18

申请人： David C. Brady ,  Isik C. Kizilyalli ,  Pradip K. Roy ,  Hem M. Vaidya

发明人： David C. Brady ,  Isik C. Kizilyalli ,  Pradip K. Roy ,  Hem M. Vaidya

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/32 ,  H01L21/76

CPC分类号： H01L21/3185 ,  H01L21/32

摘要： The present invention provides methods of manufacturing a field oxide isolation structure over a semiconductor. One of the methods includes the steps of: (1) depositing a first stack-nitride sublayer over the semiconductor at a first deposition rate and (2) subsequently depositing a second stack-nitride sublayer over the first stack-sublayer at a second deposition rate that is either greater or less than the first deposition rate. The first and second deposition rates provide first and second stack-nitride sublayers that cooperate to form a relatively thin, uniform thickness of the field oxide isolation structure over the semiconductor and provide a stress-accommodating system within the semiconductor. The varying rates of deposition and accompanying changes in mixture ratio, produce a stack that is better able to absorb stress, has greater uniformity and is far less subject to the disadvantageous phenomenon of stack-lifting, particularly encountered in semiconductor having a PADOX layer deposited thereon.

公开(公告)号：US5966627A

公开(公告)日：1999-10-12

申请号：US705936

申请日：1996-08-30

申请人： David C. Brady ,  Yaw Samuel Obeng

发明人： David C. Brady ,  Yaw Samuel Obeng

IPC分类号： C23C16/24 ,  C23C16/455 ,  H01L21/205 ,  H01L21/28 ,  H01L21/22

CPC分类号： C23C16/45561 ,  C23C16/24 ,  C23C16/455 ,  H01L21/28035 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262

摘要： A method and apparatus for the manufacture of integrated circuits including the placement of a single tube for introduction of dopant gases into a process chamber is disclosed.

摘要翻译： 公开了用于制造集成电路的方法和装置，包括将用于将掺杂剂气体引入处理室的单个管的放置。

公开(公告)号：US06246095B1

公开(公告)日：2001-06-12

申请号：US09146418

申请日：1998-09-03

申请人： David C. Brady ,  Yi Ma ,  Pradip K. Roy

发明人： David C. Brady ,  Yi Ma ,  Pradip K. Roy

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/518

摘要： This invention includes a novel synthesis of a three-step process of growing, depositing and growing Si02 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer 1.0-5.0 nm forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated Si02 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps. For light nitrogen-incorporation (

摘要翻译： 本发明包括在低压例如0.2-10托下生长，沉积和生长SiO 2的三步法的新型合成，以产生用于亚0.5微米技术的高质量，坚固和可靠的栅极氧化物。 对第一层，1.0-3.0nm进行热生长以钝化Si半导体表面。 第二沉积层1.0-5.0nm与第一生长层形成界面。 在沉积的氧化物层的合成致密化的第三步骤中，同时去除界面处的界面陷阱并且在应力容纳的存在下在Si /第一生长层界面处发生应力调制的SiO 2的生长 界面层，产生平面和应力降低的Si / SiO 2界面。 整个合成在低压（例如，0.2-10托）下进行，以减缓氧化动力学以达到超薄亚层，并且可以通过聚集所有三个步骤在单个低压炉中进行。 对于某些器件的轻氮掺入（<5％），通常由于提高的耐硼性和其他掺杂剂扩散性和热载流子特性而需要，因此在层叠氧化物合成的每个步骤期间都使用氧化剂中的N2O或NO。 平面和应力降低的Si / SiO 2界面特性是层叠氧化物的独特标志，其改善了栅极氧化物对ULSI处理的鲁棒性，导致器件参数（例如，阈值电压跨导），迁移率降低和对热载流子的耐受性降低 和福勒 - 诺德海姆的压力。

公开(公告)号：US06380606B1

公开(公告)日：2002-04-30

申请号：US09205413

申请日：1998-12-02

申请人： David C. Brady ,  Isik C. Kizilyalli ,  Pradip K. Roy ,  Hem M. Vaidya

发明人： David C. Brady ,  Isik C. Kizilyalli ,  Pradip K. Roy ,  Hem M. Vaidya

IPC分类号： H01L2900

CPC分类号： H01L21/3185 ,  H01L21/32

摘要： The present invention provides methods of manufacturing a field oxide isolation structure over a semiconductor. One of the methods includes the steps of: (1) depositing a first stack-nitride sublayer over the semiconductor at a first deposition rate and (2) subsequently depositing a second stack-nitride sublayer over the first stack-sublayer at a second deposition rate that is either greater or less than the first deposition rate. The first and second deposition rates provide first and second stack-nitride sublayers that cooperate to form a relatively thin, uniform thickness of the field oxide isolation structure over the semiconductor and provide a stress-accommodating system within the semiconductor. The varying rates of deposition and accompanying changes in mixture ratio, produce a stack that is better able to absorb stress, has greater uniformity and is far less subject to the disadvantageous phenomenon of stack-lifting, particularly encountered in semiconductor having a PADOX layer deposited thereon.

摘要翻译： 本发明提供在半导体上制造场氧化物隔离结构的方法。 其中一种方法包括以下步骤：（1）以第一沉积速率在半导体上沉积第一堆叠氮化物子层，以及（2）随后以第二沉积速率在第一堆叠子层上沉积第二堆叠氮化物层 大于或小于第一沉积速率。 第一和第二沉积速率提供第一和第二堆叠氮化物层，其协作以在半导体上形成场氧化物隔离结构的相对薄的均匀厚度，并在半导体内提供应力容纳系统。 不同的沉积速率和伴随的混合比例的变化产生更好地吸收应力的叠层，具有更大的均匀性，并且远远少于堆叠提升的不利现象，特别是在其上沉积有PADOX层的半导体中遇到 。

公开(公告)号：US6025280A

公开(公告)日：2000-02-15

申请号：US848109

申请日：1997-04-28

申请人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

发明人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

IPC分类号： C23C16/40 ,  H01L21/28 ,  H01L21/316 ,  H01L29/51

CPC分类号： H01L21/28185 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31612 ,  H01L29/513 ,  H01L29/518

摘要： This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO.sub.2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer, which contains a substantial concentration of a hydrogen isotope, such as deuterium, forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO.sub.2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO.sub.2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps. For light nitrogen-incorporation (

摘要翻译： 本发明包括在低压例如0.2-10乇下生长，沉积和生长SiO 2的三步法的新型合成，以产生用于亚0.5微米技术的高质量，坚固和可靠的栅极氧化物。 对第一层，1.0-3.0nm进行热生长以钝化Si半导体表面。 包含相当浓度的氢同位素（例如氘）的第二沉积层与第一生长层形成界面。 在沉积的氧化物层的合成致密化的第三步骤中，同时去除界面处的界面陷阱并且在应力容纳的存在下在Si /第一生长层界面处发生应力调制的SiO 2的生长 界面层，产生平面和应力降低的Si / SiO 2界面。 整个合成在低压（例如，0.2-10托）下进行，以减缓氧化动力学以达到超薄亚层，并且可以通过聚集所有三个步骤在单个低压炉中进行。 对于某些器件的轻氮掺入（<5％），通常由于提高的耐硼性和其他掺杂剂扩散性和热载流子特性而需要，因此在层叠氧化物合成的每个步骤期间都使用氧化剂中的N2O或NO。 平面和应力降低的Si / SiO 2界面特性是层叠氧化物的独特标志，其改善了栅极氧化物对ULSI处理的鲁棒性，导致器件参数（例如，阈值电压，跨导），迁移率降低和耐热性降低的散射 载体和福勒 - 诺德海姆压力。

公开(公告)号：US06281138B1

公开(公告)日：2001-08-28

申请号：US09338939

申请日：1999-06-24

申请人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

发明人： David C. Brady ,  Isik C. Kizilyalli ,  Yi Ma ,  Pradip K. Roy

IPC分类号： H01L2131

CPC分类号： H01L21/28185 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31612 ,  H01L29/513 ,  H01L29/518

摘要： This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer, which contains a substantial concentration of a hydrogen isotope, such as deuterium, forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps.

摘要翻译： 本发明包括在低压例如0.2-10乇下生长，沉积和生长SiO 2的三步法的新型合成，以产生用于亚0.5微米技术的高质量，坚固和可靠的栅极氧化物。 对第一层，1.0-3.0nm进行热生长以钝化Si半导体表面。 包含相当浓度的氢同位素（例如氘）的第二沉积层与第一生长层形成界面。 在沉积的氧化物层的合成致密化的第三步骤中，同时去除界面处的界面陷阱并且在存在应力容纳的情况下在Si /第一生长层界面处发生应力调制的SiO 2的生长 界面层，产生平面和应力降低的Si / SiO 2界面。 整个合成在低压（例如，0.2-10托）下进行，以减缓氧化动力学以达到超薄亚层，并且可以通过聚集所有三个步骤在单个低压炉中进行。

公开(公告)号：US5940736A

公开(公告)日：1999-08-17

申请号：US814670

申请日：1997-03-11

申请人： David C. Brady ,  Yi Ma ,  Pradip K. Roy

发明人： David C. Brady ,  Yi Ma ,  Pradip K. Roy

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/02

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L21/28211

摘要： This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO.sub.2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer 1.0-5.0 nm forms an interface to with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO.sub.2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO.sub.2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps. For light nitrogen-incorporation (

摘要翻译： 本发明包括在低压例如0.2-10乇下生长，沉积和生长SiO 2的三步法的新型合成，以产生用于亚0.5微米技术的高质量，坚固和可靠的栅极氧化物。 对第一层，1.0-3.0nm进行热生长以钝化Si半导体表面。 第二沉积层1.0-5.0nm形成与第一生长层的界面。 在沉积的氧化物层的合成致密化的第三步骤中，同时去除界面处的界面陷阱并且在应力容纳的存在下在Si /第一生长层界面处发生应力调制的SiO 2的生长 界面层，产生平面和应力降低的Si / SiO 2界面。 整个合成在低压（例如，0.2-10托）下进行，以减缓氧化动力学以达到超薄亚层，并且可以通过聚集所有三个步骤在单个低压炉中进行。 对于某些器件的轻氮掺入（<5％），通常由于提高的耐硼性和其他掺杂剂扩散性和热载流子特性而需要，因此在层叠氧化物合成的每个步骤期间都使用氧化剂中的N2O或NO。 平面和应力降低的Si / SiO 2界面特性是层叠氧化物的独特标志，其改善了栅极氧化物对ULSI处理的鲁棒性，导致器件参数（例如，阈值电压跨导），迁移率降低和对热载流子的耐受性降低 和福勒 - 诺德海姆的压力。