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    Methods of forming a gated device
    2.
    发明申请
    Methods of forming a gated device 有权
    形成门控装置的方法

    公开(公告)号：US20060001072A1

    公开(公告)日：2006-01-05

    申请号：US11171873

    申请日：2005-06-30

    申请人： Cem Basceri ,  H. Manning ,  Gurtej Sandhu ,  Kunal Parekh

    发明人： Cem Basceri ,  H. Manning ,  Gurtej Sandhu ,  Kunal Parekh

    IPC分类号： H01L21/8238 ,  H01L27/108 ,  H01L29/792

    CPC分类号： H01L29/4983 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

    摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括门控场效应器件，以及形成门控场效应器件的方法。 在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。 在源极/漏极区域之间的沟道区域附近接收栅极。 栅极在源极/漏极区之间具有栅极宽度。 栅极电介质被接收在沟道区域和栅极之间。 栅极电介质沿着栅极的宽度具有至少两个不同的区域。 不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。 考虑了其他方面和实现。

    Methods of forming vertical transistor structures
    3.
    发明申请
    Methods of forming vertical transistor structures 审中-公开
    形成垂直晶体管结构的方法

    公开(公告)号：US20060046392A1

    公开(公告)日：2006-03-02

    申请号：US10928467

    申请日：2004-08-26

    申请人： H. Manning ,  Kunal Parekh ,  Cem Basceri ,  Gurtej Sandhu

    发明人： H. Manning ,  Kunal Parekh ,  Cem Basceri ,  Gurtej Sandhu

    IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/425 ,  H01L21/8242

    CPC分类号： H01L29/66787 ,  H01L27/10808 ,  H01L27/10876

    摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.

    摘要翻译： 本发明包括这样的方法，其中使用成角度的注入来使源极/漏极区域注入与垂直晶体管结构的天线的顶部边缘自对准。 本发明还包括其中使用成角度的植入物以在垂直晶体管结构的栅极下注入掺杂剂的方法。 根据本发明的方法形成的垂直晶体管结构可以结合到各种类型的集成电路中，包括例如DRAM阵列。

    Gated field effect devices
    4.
    发明申请
    Gated field effect devices 失效
    门控场效应器件

    公开(公告)号：US20060038244A1

    公开(公告)日：2006-02-23

    申请号：US11253461

    申请日：2005-10-19

    申请人： Cem Basceri ,  H. Manning ,  Gurtej Sandhu ,  Kunal Parekh

    发明人： Cem Basceri ,  H. Manning ,  Gurtej Sandhu ,  Kunal Parekh

    IPC分类号： H01L29/94

    CPC分类号： H01L29/4983 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

    摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括门控场效应器件，以及形成门控场效应器件的方法。 在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。 在源极/漏极区域之间的沟道区域附近接收栅极。 栅极在源极/漏极区之间具有栅极宽度。 栅极电介质被接收在沟道区域和栅极之间。 栅极电介质沿着栅极的宽度具有至少两个不同的区域。 不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。 考虑了其他方面和实现。

    Gated field effect devices
    6.
    发明申请
    Gated field effect devices 有权
    门控场效应器件

    公开(公告)号：US20050269648A1

    公开(公告)日：2005-12-08

    申请号：US10861744

    申请日：2004-06-04

    申请人： Cem Basceri ,  H. Montgomery Manning ,  Gurtej Sandhu ,  Kunal Parekh

    发明人： Cem Basceri ,  H. Montgomery Manning ,  Gurtej Sandhu ,  Kunal Parekh

    IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/4983 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

    摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括门控场效应器件，以及形成门控场效应器件的方法。 在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。 在源极/漏极区域之间的沟道区域附近接收栅极。 栅极在源极/漏极区之间具有栅极宽度。 栅极电介质被接收在沟道区域和栅极之间。 栅极电介质沿着栅极的宽度具有至少两个不同的区域。 不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。 考虑了其他方面和实现。

    Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
    7.
    发明申请
    Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 失效

    公开(公告)号：US20070015358A1

    公开(公告)日：2007-01-18

    申请号：US11525707

    申请日：2006-09-21

    申请人： Cem Basceri ,  Gurtej Sandhu ,  H. Manning

    发明人： Cem Basceri ,  Gurtej Sandhu ,  H. Manning

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76823 ,  H01L21/28512 ,  H01L21/76895 ,  Y10T428/12542

    摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

    Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
    8.
    发明申请
    Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 有权

    公开(公告)号：US20060046473A1

    公开(公告)日：2006-03-02

    申请号：US10932218

    申请日：2004-09-01

    申请人： Cem Basceri ,  Gurtej Sandhu ,  H. Manning

    发明人： Cem Basceri ,  Gurtej Sandhu ,  H. Manning

    IPC分类号： H01L29/06

    CPC分类号： H01L21/76823 ,  H01L21/28512 ,  H01L21/76895 ,  Y10T428/12542

    摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

    Methods of forming field effect transistors
    9.
    发明申请
    Methods of forming field effect transistors 有权

    公开(公告)号：US20060040437A1

    公开(公告)日：2006-02-23

    申请号：US10925100

    申请日：2004-08-23

    申请人： Gurtej Sandhu ,  H. Manning ,  Cem Basceri

    发明人： Gurtej Sandhu ,  H. Manning ,  Cem Basceri

    IPC分类号： H01L21/337

    CPC分类号： H01L29/66666 ,  H01L29/7827

    摘要： A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided laterally between the mass of material and the semiconductive material. The space comprises an outermost portion and a portion immediately adjacent thereto. The outermost portion has a maximum lateral width which is greater than that of the adjacent portion. Gate dielectric material and conductive gate material are formed within the space. The gate dielectric material and the conductive gate material in combination fill the adjacent portion of the space but do not fill the outermost portion of the space. At least the conductive gate material is etched from at least a majority of the outermost portion of the space. Source/drain regions are formed operatively proximate the conductive gate material and the semiconductive material is used as a channel region of the field effect transistor.

    Methods of forming field effect transistors
    10.
    发明申请
    Methods of forming field effect transistors 有权

    公开(公告)号：US20060258071A1

    公开(公告)日：2006-11-16

    申请号：US11490681

    申请日：2006-07-21

    申请人： Gurtej Sandhu ,  H. Manning ,  Cem Basceri

    发明人： Gurtej Sandhu ,  H. Manning ,  Cem Basceri

    IPC分类号： H01L21/337

    CPC分类号： H01L29/66666 ,  H01L29/7827

    摘要： A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided laterally between the mass of material and the semiconductive material. The space comprises an outermost portion and a portion immediately adjacent thereto. The outermost portion has a maximum lateral width which is greater than that of the adjacent portion. Gate dielectric material and conductive gate material are formed within the space. The gate dielectric material and the conductive gate material in combination fill the adjacent portion of the space but do not fill the outermost portion of the space. At least the conductive gate material is etched from at least a majority of the outermost portion of the space. Source/drain regions are formed operatively proximate the conductive gate material and the semiconductive material is used as a channel region of the field effect transistor.