公开(公告)号：US20120075024A1

公开(公告)日：2012-03-29

申请号：US13308923

申请日：2011-12-01

申请人： Chan-Kyung KIM

发明人： Chan-Kyung KIM

IPC分类号： H03K3/03

CPC分类号： H03K3/354 ,  G11C7/22 ,  G11C7/222

摘要： One embodiment of the oscillator includes a first starved inverter and a second starved inverter. An inner inverter of the second starved inverter is cross-coupled to an inner inverter of the first starved inverter. The oscillator further includes a first inverter connected to output of the inner inverter of the first starved inverter, and a second inverter connected to output of the inner inverter of the second starved inverter.

摘要翻译： 振荡器的一个实施例包括第一饥饿逆变器和第二饥饿逆变器。 第二饥饿逆变器的内逆变器与第一饥饿逆变器的内逆变器交叉耦合。 振荡器还包括连接到第一饥饿逆变器的内逆变器的输出的第一反相器和连接到第二饥饿逆变器的内逆变器的输出的第二反相器。

公开(公告)号：US20150364178A1

公开(公告)日：2015-12-17

申请号：US14677991

申请日：2015-04-03

申请人： Chan-Kyung KIM ,  Kee-Won KWON ,  Su-A KIM ,  Chul-Woo PARK ,  Jae-Youn YOUN

发明人： Chan-Kyung KIM ,  Kee-Won KWON ,  Su-A KIM ,  Chul-Woo PARK ,  Jae-Youn YOUN

IPC分类号： G11C11/16 ,  G11C5/08

CPC分类号： G11C11/16 ,  G11C5/025 ,  G11C5/08 ,  G11C7/065 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/4091 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2213/79 ,  G11C2213/82

摘要： A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.

摘要翻译： 电阻型存储器件的存储核心至少包括耦合到位线的第一电阻型存储单元，第一电阻转换器和位线读出放大器。 第一电阻转换器在第一节点处耦合到位线。 第一电阻转换器基于读列选择信号将第一电阻型存储单元的电阻转换成相应的电压。 位线读出放大器耦合到第一节点处的位线，并且耦合到第二节点处的互补位线。 位线检测放大器响应于感测控制信号而感测和放大位线和互补位线的电压差。

公开(公告)号：US20150035032A1

公开(公告)日：2015-02-05

申请号：US14310114

申请日：2014-06-20

申请人： Dong-Seok KANG ,  Chan-Kyung KIM

发明人： Dong-Seok KANG ,  Chan-Kyung KIM

IPC分类号： H01L27/22

CPC分类号： H01L27/228 ,  G11C7/1075 ,  G11C7/14 ,  G11C7/18 ,  G11C8/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/79 ,  G11C2213/82

摘要： A memory cell array of a nonvolatile semiconductor memory device is provided which includes a first memory cell including a first variable resistance element and a first access transistor connected to each other, and having a first node connected to a first bit line and one end of the first variable resistance element and a second node connected to a second bit line and one end of the first access transistor; and a second memory cell including a second variable resistance element and a second access transistor connected to each other, and having a first node connected to the second bit line and one end of the second variable resistance element and a second node connected to one end of the second access transistor, wherein the first and second access transistors are connected to first and second word lines, respectively.

摘要翻译： 提供了一种非易失性半导体存储器件的存储单元阵列，其包括第一存储单元，该第一存储单元包括彼此连接的第一可变电阻元件和第一存取晶体管，并且具有连接到第一位线和第一存储晶体管的一端的第一节点 第一可变电阻元件和连接到第一存取晶体管的第二位线和一端的第二节点; 以及第二存储单元，包括彼此连接的第二可变电阻元件和第二存取晶体管，并且具有连接到第二位线和第二可变电阻元件的一端的第一节点和连接到第二可变电阻元件的一端的第二节点 第二存取晶体管，其中第一和第二存取晶体管分别连接到第一和第二字线。

公开(公告)号：US20070160113A1

公开(公告)日：2007-07-12

申请号：US11566658

申请日：2006-12-04

申请人： Chan-Kyung KIM ,  Young-Hyun JUN

发明人： Chan-Kyung KIM ,  Young-Hyun JUN

IPC分类号： G01K7/00

CPC分类号： G01K7/32 ,  G01K7/01 ,  G11C7/04

摘要： Provided are a temperature sensor using a ring oscillator and temperature detection method using the same. One embodiment of the temperature sensor includes a first pulse generator, a second pulse generator, and a counter. The first pulse generator includes a first ring oscillator and generates a first clock signal having a variable period according to a change in temperature. The second pulse generator includes a second ring oscillator and generates a second clock signal having a fixed period. The counter counts a pulse width of the first clock signal as a function of a pulse width of the second clock signal and generates a temperature code.

摘要翻译： 提供了使用环形振荡器的温度传感器和使用其的温度检测方法。 温度传感器的一个实施例包括第一脉冲发生器，第二脉冲发生器和计数器。 第一脉冲发生器包括第一环形振荡器，并根据温度变化产生具有可变周期的第一时钟信号。 第二脉冲发生器包括第二环形振荡器并产生具有固定周期的第二时钟信号。 计数器根据第二时钟信号的脉冲宽度对第一时钟信号的脉冲宽度进行计数，并产生温度代码。

公开(公告)号：US20160027488A1

公开(公告)日：2016-01-28

申请号：US14722031

申请日：2015-05-26

申请人： Chan-Kyung KIM

发明人： Chan-Kyung KIM

IPC分类号： G11C11/16

CPC分类号： G11C11/1673 ,  G11C7/14 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659

摘要： A resistive memory device may include first and second resistive memory cells, a reference current generator, and first and second bitline sense amplifiers. The reference current generator may be configured to apply the first and second reference currents to a first common node. A total reference current of the first reference current and the second reference current provided to the first common node may be divided into a first sensing current and a second sensing current by the first common node. The first and second sensing currents may be provided to the first and second bitline sense amplifiers by the first common node, respectively. The first and second bitline sense amplifiers may be configured to sense first data of the first resistive memory cell and second data of the second resistive memory cell based on the first and second sensing currents, respectively.

摘要翻译： 电阻式存储器件可以包括第一和第二电阻存储器单元，参考电流发生器以及第一和第二位线读出放大器。 参考电流发生器可以被配置为将第一和第二参考电流施加到第一公共节点。 提供给第一公共节点的第一参考电流和第二参考电流的总参考电流可以被第一公共节点划分为第一感测电流和第二感测电流。 第一和第二感测电流可以分别由第一公共节点提供给第一和第二位线读出放大器。 第一和第二位线读出放大器可以被配置为分别基于第一和第二感测电流来感测第一电阻存储器单元的第一数据和第二电阻存储器单元的第二数据。

公开(公告)号：US20150364187A1

公开(公告)日：2015-12-17

申请号：US14660530

申请日：2015-03-17

申请人： Chan-Kyung KIM ,  Kee-Won KWON

发明人： Chan-Kyung KIM ,  Kee-Won KWON

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C2013/0054

摘要： A resistive memory device may include a resistive cell array and an on-chip resistance measurement circuit. The resistive cell array may include a plurality of resistive memory cells. The on-chip resistance measurement circuit may be configured to generate a first current and a second current greater or less than the first current based on a cell current corresponding to a cell resistance of a first memory cell of the resistive memory cells, and to generate first and second digital signals based on the first and second current, respectively.

摘要翻译： 电阻式存储器件可以包括电阻单元阵列和片上电阻测量电路。 电阻单元阵列可以包括多个电阻存储单元。 片上电阻测量电路可以被配置为基于与电阻性存储器单元的第一存储单元的单元电阻对应的单元电流来产生大于或小于第一电流的第一电流和第二电流，并且生成 分别基于第一和第二电流的第一和第二数字信号。

公开(公告)号：US20070160114A1

公开(公告)日：2007-07-12

申请号：US11566664

申请日：2006-12-04

申请人： Chan-Kyung KIM

发明人： Chan-Kyung KIM

IPC分类号： G01K7/00

CPC分类号： G01K7/01 ,  G01K7/00 ,  G11C7/04

摘要： Provided are a temperature sensor for generating a sectional temperature code and sectional temperature detection method. In one embodiment, the temperature sensor includes a plurality of serially connected fixed delay cells inputting a temperature detection signal and delaying the temperature detection signal, a variable delay cell inputting the temperature detection signal and delaying the temperature detection signal; and a sectional discrimination logic unit latching outputs of the fixed delay cells in response to the variable delay cells and generating the sectional temperature code. The sectional discrimination logic unit discriminates the sectional temperatures based on temperatures where an output of the variable delay cell meets each of outputs of the fixed delay cells according to the change in the temperature, and generates temperature codes corresponding to the sectional temperatures.

摘要翻译： 提供一种用于产生截面温度代码和截面温度检测方法的温度传感器。 在一个实施例中，温度传感器包括输入温度检测信号并延迟温度检测信号的多个串联连接的固定延迟单元，输入温度检测信号并延迟温度检测信号的可变延迟单元; 以及截面鉴别逻辑单元，其响应于所述可变延迟单元来锁存所述固定延迟单元的输出并产生所述截面温度代码。 截面识别逻辑单元根据温度变化，根据可变延迟单元的输出与固定延迟单元的输出相遇的温度来区分截面温度，并生成与截面温度对应的温度代码。

公开(公告)号：US20180107406A1

公开(公告)日：2018-04-19

申请号：US15603255

申请日：2017-05-23

申请人： SEONG-IL O ,  Nam Sung KIM ,  Young-Hoon SON ,  Chan-Kyung KIM ,  Ho-Young SONG ,  Jung Ho AHN ,  Sang-Joon HWANG

发明人： SEONG-IL O ,  Nam Sung KIM ,  Young-Hoon SON ,  Chan-Kyung KIM ,  Ho-Young SONG ,  Jung Ho AHN ,  Sang-Joon HWANG

IPC分类号： G06F3/06 ,  G06F13/16

CPC分类号： G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1673

摘要： A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

公开(公告)号：US20140169086A1

公开(公告)日：2014-06-19

申请号：US14105782

申请日：2013-12-13

申请人： Chan-Kyung KIM ,  Dong-Min KIM ,  Hong-Sun HWANG

发明人： Chan-Kyung KIM ,  Dong-Min KIM ,  Hong-Sun HWANG

IPC分类号： G11C11/16

CPC分类号： G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1697

摘要： A memory device includes a cell array and a common source line compensation circuit. The cell array includes a plurality of normal cell units connected between a plurality of bit lines and one common source line, respectively. The common source line compensation circuit supplies a plurality of compensation write currents to the common source line to compensate for a plurality of write currents concurrently input into or output from the common source line through the normal cell units.

摘要翻译： 存储器件包括单元阵列和公共源极线补偿电路。 单元阵列包括分别连接在多个位线和一个公共源极线之间的多个正常单元单元。 公共源极线补偿电路向公共源极线提供多个补偿写入电流，以补偿通过正常单元单元同时输入到共用源极线或从共模源极线输出的多个写入电流。