公开(公告)号：US20080296649A1

公开(公告)日：2008-12-04

申请号：US11944260

申请日：2007-11-21

申请人： Chang-Woo OH ,  Dong-Gun PARK ,  Jeong-Dong CHOE ,  Kyoung-Hwan YEO

发明人： Chang-Woo OH ,  Dong-Gun PARK ,  Jeong-Dong CHOE ,  Kyoung-Hwan YEO

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L29/66651 ,  H01L27/10873 ,  H01L29/0653 ,  H01L29/66659

摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

摘要翻译： 半导体器件采用非对称埋层绝缘层及其制造方法。 半导体器件包括下半导体衬底。 上硅图案位于下半导体衬底上。 上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。 栅电极与上硅图案电绝缘，并且在沟道区域上相交。 位线和单元电容器分别电连接到源极区域和漏极区域。 掩埋绝缘层插入在漏区和下半导体衬底之间。 掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。

公开(公告)号：US20080032469A1

公开(公告)日：2008-02-07

申请号：US11764751

申请日：2007-06-18

申请人： Chang-Woo OH ,  Dong-Gun PARK ,  Dong-Won KIM ,  Jeong-Dong CHOE

发明人： Chang-Woo OH ,  Dong-Gun PARK ,  Dong-Won KIM ,  Jeong-Dong CHOE

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78687 ,  Y10S438/933

摘要： A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.

摘要翻译： 提供具有场效应晶体管的半导体器件及其形成方法。 半导体器件优选地包括设置在衬底的预定区域上的器件有源图案。 栅电极优选地跨过器件有源图案，由栅极绝缘层插入。 支撑图案优选地插入在器件活性图案和基底之间。 支撑图案可以设置在栅电极下方。 填充绝缘图案优选地设置在装置活性图案和填充绝缘图案之间。 填充绝缘图案可以设置在源极/漏极区域下方。 栅电极下方的器件有源图案优选由具有比硅晶格宽的晶格宽度的应变硅形成。

公开(公告)号：US20080145989A1

公开(公告)日：2008-06-19

申请号：US12040636

申请日：2008-02-29

申请人： Chang-Woo OH ,  Dong-Gun PARK ,  Jeong-Dong CHOE ,  Min-Sang KIM ,  Sung-Min KIM

发明人： Chang-Woo OH ,  Dong-Gun PARK ,  Jeong-Dong CHOE ,  Min-Sang KIM ,  Sung-Min KIM

IPC分类号： H01L29/06

CPC分类号： H01L21/823481 ,  H01L21/76283 ,  H01L29/1079 ,  H01L29/78

摘要： Embodiments of the invention include a partially insulated field effect transistor and a method of fabricating the same. According to some embodiments, a semiconductor substrate is formed by sequentially stacking a bottom semiconductor layer, a sacrificial layer, and a top semiconductor layer. The sacrificial layer may be removed to form a buried gap region between the bottom semiconductor layer and the top semiconductor layer. Then, a transistor may be formed on the semiconductor substrate. The sacrificial layer may be a crystalline semiconductor formed by an epitaxial growth technology.

摘要翻译： 本发明的实施例包括部分绝缘的场效应晶体管及其制造方法。 根据一些实施例，通过顺序堆叠底部半导体层，牺牲层和顶部半导体层来形成半导体衬底。 可以去除牺牲层以在底部半导体层和顶部半导体层之间形成掩埋间隙区域。 然后，可以在半导体衬底上形成晶体管。 牺牲层可以是通过外延生长技术形成的晶体半导体。

公开(公告)号：US20070210368A1

公开(公告)日：2007-09-13

申请号：US11683364

申请日：2007-03-07

申请人： Eun-Suk CHO ,  Jong-Jin LEE ,  Dong-Gun PARK ,  Jeong-Dong CHOE

发明人： Eun-Suk CHO ,  Jong-Jin LEE ,  Dong-Gun PARK ,  Jeong-Dong CHOE

IPC分类号： H01L21/3205 ,  H01L29/76

CPC分类号： H01L29/7885 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42332 ,  H01L29/7851 ,  H01L29/792

摘要： A gate structure in a semiconductor device includes a tunnel insulation layer disposed on a substrate, a first charge trapping layer disposed on the tunnel insulation layer, a second charge trapping layer disposed on the first charge trapping layer, a dielectric layer disposed to cover the second charge trapping layer, and a conductive layer pattern disposed on the dielectric layer. The first charge trapping layer includes charge trapping sites for storing charges therein. The second charge trapping layer includes nanocrystals. The semiconductor device including the gate structure may have a sufficiently wide programming/erasing window and an improved data retention capability.

摘要翻译： 半导体器件中的栅极结构包括设置在衬底上的隧道绝缘层，设置在隧道绝缘层上的第一电荷俘获层，设置在第一电荷俘获层上的第二电荷俘获层，设置成覆盖第二电荷俘获层的电介质层 电荷捕获层和设置在电介质层上的导电层图案。 第一电荷俘获层包括用于在其中存储电荷的电荷俘获位置。 第二电荷俘获层包括纳米晶体。 包括栅极结构的半导体器件可以具有足够宽的编程/擦除窗口和改进的数据保持能力。

公开(公告)号：US20120007165A1

公开(公告)日：2012-01-12

申请号：US13181281

申请日：2011-07-12

申请人： Myoung-Bum LEE ,  Jae-Hwang SIM ,  In-Sun PARK ,  Jin-Gi HONG ,  Ju-Seon GOO ,  Seung-Bae PARK ,  Seung-Yup LEE ,  Du-Heon SONG ,  Jeong-Dong CHOE ,  Seok-Won LEE

发明人： Myoung-Bum LEE ,  Jae-Hwang SIM ,  In-Sun PARK ,  Jin-Gi HONG ,  Ju-Seon GOO ,  Seung-Bae PARK ,  Seung-Yup LEE ,  Du-Heon SONG ,  Jeong-Dong CHOE ,  Seok-Won LEE

IPC分类号： H01L29/788 ,  H01L27/088

CPC分类号： H01L29/7881 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor device includes a substrate, a plurality of gate structures, a first insulating interlayer pattern, and a second insulation layer pattern. The substrate has an active region and a field region, each of the active region and the field region extends in a first direction, and the active region and the field region are alternately and repeatedly arranged in a second direction substantially perpendicular to the first direction. The gate structures are spaced apart from each other in the first direction, each of the gate structures extends in the second direction. The first insulation layer pattern is formed on a portion of a sidewall of each gate structure. The second insulation layer pattern covers the gate structures and the first insulation layer pattern, and has an air tunnel between the gate structures, the air tunnel extending in the second direction.

摘要翻译： 半导体器件包括衬底，多个栅极结构，第一绝缘层间图案和第二绝缘层图案。 基板具有有源区域和场区域，有源区域和场区域中的每一个沿着第一方向延伸，并且有源区域和场区域在基本上垂直于第一方向的第二方向上交替地和重复地布置。 栅极结构在第一方向上彼此间隔开，每个栅极结构沿第二方向延伸。 第一绝缘层图案形成在每个栅极结构的侧壁的一部分上。 第二绝缘层图案覆盖栅极结构和第一绝缘层图案，并且在栅极结构之间具有沿第二方向延伸的空气通道的空气通道。