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    Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices
    1.
    发明授权
    Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices 有权
    具有后编程操作电阻漂移饱和的多电平单元相变存储器件，采用这种器件的存储器系统以及读取存储器件的方法

    公开(公告)号：US07778079B2

    公开(公告)日：2010-08-17

    申请号：US12079892

    申请日：2008-03-28

    申请人： Chang-Wook Jeong ,  Dae-Hwan Kang ,  Hyeong-Jun Kim ,  Jae-Min Shin ,  Seung-Pil Ko

    发明人： Chang-Wook Jeong ,  Dae-Hwan Kang ,  Hyeong-Jun Kim ,  Jae-Min Shin ,  Seung-Pil Ko

    IPC分类号： G11C16/06

    CPC分类号： G11C11/5678 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078

    摘要： In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming current in a programming operation; and a modification circuit that modifies the resistance of the memory cell following a programming operation of the memory cell to vary the resistance of the memory cell from the initial resistance to a second resistance by applying a saturation current in a saturation operation. Each memory cell is connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation, that is used to apply the saturation current to the corresponding memory cell in the saturation operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a subsequent read operation.

    摘要翻译： 在存储器件和其编程方法中，存储器件包括：多个存储器单元，每个存储器单元包括电阻可变材料，该电阻可变材料具有响应于在一个应用编程电流中确定的初始电阻 编程操作; 以及修改电路，其在存储单元的编程操作之后修改存储单元的电阻，以通过在饱和运算中施加饱和电流来将存储单元的电阻从初始电阻改变为第二电阻。 每个存储单元连接到存储器件的导线，该导线用于施加编程电流以对编程操作中对应的存储单元的电阻进行编程，用于将饱和电流施加到相应的存储单元中 饱和操作，并且用于在随后的读取操作中应用读取电流来读取相应存储器单元的电阻。

    Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices
    2.
    发明申请
    Multiple level cell phase-change memory devices having post-programming operation resistance drift saturation, memory systems employing such devices and methods of reading memory devices 有权
    具有后编程操作电阻漂移饱和的多电平单元相变存储器件，采用这种器件的存储器系统以及读取存储器件的方法

    公开(公告)号：US20090016099A1

    公开(公告)日：2009-01-15

    申请号：US12079892

    申请日：2008-03-28

    申请人： Chang-Wook Jeong ,  Dae-Hwan Kang ,  Hyeong-Jun Kim ,  Jae-Min Shin ,  Seung-Pil Ko

    发明人： Chang-Wook Jeong ,  Dae-Hwan Kang ,  Hyeong-Jun Kim ,  Jae-Min Shin ,  Seung-Pil Ko

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/5678 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078

    摘要： In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming current in a programming operation; and a modification circuit that modifies the resistance of the memory cell following a programming operation of the memory cell to vary the resistance of the memory cell from the initial resistance to a second resistance by applying a saturation current in a saturation operation. Each memory cell is connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation, that is used to apply the saturation current to the corresponding memory cell in the saturation operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a subsequent read operation.

    摘要翻译： 在存储器件和其编程方法中，存储器件包括：多个存储器单元，每个存储器单元包括电阻可变材料，该电阻可变材料具有响应于在一个应用编程电流中确定的初始电阻 编程操作; 以及修改电路，其在存储单元的编程操作之后修改存储单元的电阻，以通过在饱和运算中施加饱和电流来将存储单元的电阻从初始电阻改变为第二电阻。 每个存储单元连接到存储器件的导线，该导线用于施加编程电流以对编程操作中对应的存储单元的电阻进行编程，用于将饱和电流施加到相应的存储单元中 饱和操作，并且用于在随后的读取操作中应用读取电流来读取相应存储器单元的电阻。

    Multiple level cell phase-change memory devices having controlled resistance drift parameter, memory systems employing such devices and methods of reading memory devices
    3.
    发明申请
    Multiple level cell phase-change memory devices having controlled resistance drift parameter, memory systems employing such devices and methods of reading memory devices 有权
    具有受控电阻漂移参数的多电平单元相变存储器件，采用这种器件的存储器系统以及读取存储器件的方法

    公开(公告)号：US20080316804A1

    公开(公告)日：2008-12-25

    申请号：US12079886

    申请日：2008-03-28

    申请人： Chang-Wook Jeong ,  Dae-Hwan Kang ,  Hyeong-Jun Kim ,  Seung-Pil Ko ,  Dong-Won Lim

    发明人： Chang-Wook Jeong ,  Dae-Hwan Kang ,  Hyeong-Jun Kim ,  Seung-Pil Ko ,  Dong-Won Lim

    IPC分类号： G11C11/00

    CPC分类号： G11C11/5678 ,  G11C11/56 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/3427

    摘要： In a method of controlling resistance drift in a memory cell of a resistance-changeable material memory device, the resistance changeable material in the memory cell is treated so that a drift parameter for the memory cell is less than about 0.18, wherein a change in resistance of a memory cell over the time period is determined according to the relationship: Rdrift=Rinitial×tα; where Rdrift represents a final resistance of the memory cell following the time period, Rinitial represents the initial resistance of the memory cell following the programming operation, t represents the time period; and α represents the drift parameter.

    摘要翻译： 在电阻可变材料存储装置的存储单元中控制电阻漂移的方法中，对存储单元中的电阻变化材料进行处理，使得存储单元的漂移参数小于约0.18，其中电阻变化 根据以下关系确定该时间段内的存储单元：<？in-line-formula description =“In-line Formulas”end =“lead”？> Rdrift = Rinitialxtalpha; <？in-line-formula description = “In-Line Formulas”end =“tail”？>其中Rdrift表示在时间段之后的存储单元的最终电阻，Rinitial表示编程操作之后的存储单元的初始电阻，t表示时间段; 而alpha表示漂移参数。

    Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices
    5.
    发明申请
    Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices 有权
    具有预读取操作电阻漂移恢复的多电平单元相变存储器件，采用这种器件的存储器系统以及读取存储器件的方法

    公开(公告)号：US20080266942A1

    公开(公告)日：2008-10-30

    申请号：US12079869

    申请日：2008-03-28

    申请人： Chang-Wook Jeong ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

    发明人： Chang-Wook Jeong ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  Y10S977/754

    摘要： A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

    摘要翻译： 存储器件包括多个存储器单元，每个存储器单元包括存储单元材料，该存储单元材料具有响应于编程操作中所施加的编程电流而确定的初始电阻，存储单元的电阻从初始电阻变化 编程操作之后的时间段，并且每个存储器单元连接到存储器件的传导线，其用于在编程操作中应用编程电流来对相应的存储器单元的电阻进行编程，并且用于应用编程 读取电流以读取读取操作中的相应存储单元的电阻。 修改电路修改为读取操作选择的多个存储单元的存储单元的电阻，以在存储单元的读取操作之前将其电阻返回到接近初始电阻。

    Magnetic Random Access Memory Cells Having Split Subdigit Lines Having Cladding Layers Thereon and Methods of Fabricating the Same
    7.
    发明申请
    Magnetic Random Access Memory Cells Having Split Subdigit Lines Having Cladding Layers Thereon and Methods of Fabricating the Same 失效
    磁性随机存取存储器单元分割具有包层的子数字线及其制作方法

    公开(公告)号：US20080160643A1

    公开(公告)日：2008-07-03

    申请号：US12048082

    申请日：2008-03-13

    申请人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

    发明人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

    IPC分类号： H01L43/12

    CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L43/08 ,  H01L43/12

    摘要： Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

    摘要翻译： 磁性RAM单元具有由包覆层包围的分割的子数字线，并且提供其制造方法。 磁性RAM单元包括在半导体衬底上形成的第一和第二子数字线。 只有第一子数字线的底表面和外侧壁被第一覆层图案覆盖。 此外，仅第二子数字线的底表面和外侧壁被第二包层图案覆盖。 第一子数字线的外侧壁位于远离第二子数字线的位置，第二子数字线的外侧壁位于第一子数字线的远侧。 还提供了制造磁性RAM单元的方法。

    Magnetic random access memory devices including heat generating layers and related methods
    8.
    发明授权
    Magnetic random access memory devices including heat generating layers and related methods 有权
    磁性随机存取存储器件包括发热层和相关方法

    公开(公告)号：US07092283B2

    公开(公告)日：2006-08-15

    申请号：US10795600

    申请日：2004-03-08

    申请人： Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hyeong-Jun Kim ,  Jae-Hyun Park

    发明人： Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hyeong-Jun Kim ,  Jae-Hyun Park

    IPC分类号： G11C11/00 ,  G11C11/14

    CPC分类号： H01L43/08 ,  G11C11/15 ,  G11C11/1675 ,  H01L27/228

    摘要： A magnetic random access memory device may include a first electrode on a substrate, a magnetic tunneling junction element electrically connected to the electrode, and a second electrode electrically connected to the first electrode through the magnetic tunneling junction element. In addition, a heat generating layer may be electrically connected in series between the first and second electrodes, and the heat generating layer may provide a relatively high resistance with respect to electrical current flow. Related methods are also discussed.

    摘要翻译： 磁性随机存取存储器件可以包括在衬底上的第一电极，电连接到电极的磁性隧道接合元件，以及通过磁性隧道结接合元件电连接到第一电极的第二电极。 此外，发热层可以串联地电连接在第一和第二电极之间，并且发热层可以相对于电流流动提供相对较高的电阻。 还讨论了相关方法。

    Magnetic random access memory cells having split subdigit lines having cladding layers thereon and methods of fabricating the same
    10.
    发明授权
    Magnetic random access memory cells having split subdigit lines having cladding layers thereon and methods of fabricating the same 失效
    磁性随机存取存储单元具有其上具有覆层的分割子数据线及其制造方法

    公开(公告)号：US07569401B2

    公开(公告)日：2009-08-04

    申请号：US12048082

    申请日：2008-03-13

    申请人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

    发明人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

    IPC分类号： H01L21/00

    CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L43/08 ,  H01L43/12

    摘要： Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

    摘要翻译： 磁性RAM单元具有由包覆层包围的分割的子数字线，并且提供其制造方法。 磁性RAM单元包括在半导体衬底上形成的第一和第二子数字线。 只有第一子数字线的底表面和外侧壁被第一覆层图案覆盖。 此外，仅第二子数字线的底表面和外侧壁被第二包层图案覆盖。 第一子数字线的外侧壁位于远离第二子数字线的位置，第二子数字线的外侧壁位于第一子数字线的远侧。 还提供了制造磁性RAM单元的方法。