公开(公告)号：US08232613B2

公开(公告)日：2012-07-31

申请号：US12926227

申请日：2010-11-03

申请人： Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

发明人： Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

IPC分类号： H01L31/119

CPC分类号： H01L29/7848 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.

摘要翻译： 示例性实施例涉及形成锗（锗）硅化物层的方法，包括锗硅化物层的半导体器件以及制造半导体器件的方法。 根据示例性实施方案的形成锗硅化物层的方法可以包括在硅锗（SiGe）层上形成包括钒（V）的金属层。 金属层可以具有多层结构，并且还可以包括铂（Pt）和镍（Ni）中的至少一种。 金属层可以退火以形成硅化锗层。 可以使用激光尖峰退火（LSA）方法进行退火。

公开(公告)号：US20110049587A1

公开(公告)日：2011-03-03

申请号：US12926227

申请日：2010-11-03

申请人： Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

发明人： Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.

摘要翻译： 示例性实施例涉及形成锗（锗）硅化物层的方法，包括锗硅化物层的半导体器件以及制造半导体器件的方法。 根据示例性实施方案的形成锗硅化物层的方法可以包括在硅锗（SiGe）层上形成包括钒（V）的金属层。 金属层可以具有多层结构，并且还可以包括铂（Pt）和镍（Ni）中的至少一种。 金属层可以退火以形成硅化锗层。 可以使用激光尖峰退火（LSA）方法进行退火。

公开(公告)号：US20090146183A1

公开(公告)日：2009-06-11

申请号：US12078750

申请日：2008-04-04

申请人： Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

发明人： Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/335

CPC分类号： H01L29/7848 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.

摘要翻译： 示例性实施例涉及形成锗（锗）硅化物层的方法，包括锗硅化物层的半导体器件以及制造半导体器件的方法。 根据示例性实施方案的形成锗硅化物层的方法可以包括在硅锗（SiGe）层上形成包括钒（V）的金属层。 金属层可以具有多层结构，并且还可以包括铂（Pt）和镍（Ni）中的至少一种。 金属层可以退火以形成硅化锗层。 可以使用激光尖峰退火（LSA）方法进行退火。

公开(公告)号：US07863142B2

公开(公告)日：2011-01-04

申请号：US12078750

申请日：2008-04-04

申请人： Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

发明人： Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.

公开(公告)号：US20080272366A1

公开(公告)日：2008-11-06

申请号：US12010806

申请日：2008-01-30

申请人： Chang-wook Moon ,  Joong S. Jeon ,  Jung-hyun Lee ,  Nae-in Lee ,  Yeon-sik Park ,  Hwa-sung Rhee ,  Ho Lee ,  Se-young Cho ,  Suk-pil Kim

发明人： Chang-wook Moon ,  Joong S. Jeon ,  Jung-hyun Lee ,  Nae-in Lee ,  Yeon-sik Park ,  Hwa-sung Rhee ,  Ho Lee ,  Se-young Cho ,  Suk-pil Kim

IPC分类号： H01L29/12 ,  H01L21/336

CPC分类号： H01L29/66439 ,  B82Y10/00 ,  B82Y15/00 ,  H01L21/02356 ,  H01L21/02365 ,  H01L21/02601 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/66742 ,  H01L29/7839 ,  H01L29/78684 ,  H01L29/78696 ,  H01L51/426 ,  H01L2221/1094

摘要： A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate oxide layer formed on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate oxide layer between the source electrode and the drain electrode.

摘要翻译： 提供具有至少一个Ge纳米棒的场效应晶体管和制造场效应晶体管的方法。 场效应晶体管可以包括形成在硅衬底上的栅氧化层，至少一个纳米棒嵌入在其两端被暴露的栅极氧化层中，源电极和漏极连接到至少一个Ge纳米棒的相对侧 以及形成在源电极和漏电极之间的栅氧化层上的栅电极。

公开(公告)号：US20070117297A1

公开(公告)日：2007-05-24

申请号：US11656717

申请日：2007-01-23

申请人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

发明人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

IPC分类号： H01L21/8234

CPC分类号： H01L29/66916 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78687 ,  H01L29/802

摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2

摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小 峰值电平朝向未应变硅活性层的表面。 峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。 更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

公开(公告)号：US07642140B2

公开(公告)日：2010-01-05

申请号：US11656717

申请日：2007-01-23

申请人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

发明人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

IPC分类号： H01L21/84

CPC分类号： H01L29/66916 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78687 ,  H01L29/802

摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2

摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si1-xGex层也设置在电绝缘层和未应变硅有源层之间。 Si1-xGex层与未应变的硅有源层形成第一结，并且其中Ge的分级浓度在从峰值电平朝向未应变硅有源层的表面延伸的第一方向上单调减小。 峰值Ge浓度水平大于x = 0.15，并且Si1-xGex层中的Ge浓度在第一结处从峰值水平变化到小于约x = 0.1的水平。 Ge在第一结处的浓度可能是突然的。 更优选地，Si1-xGex层中的Ge的浓度从0.2

公开(公告)号：US20050230676A1

公开(公告)日：2005-10-20

申请号：US11141275

申请日：2005-06-01

申请人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

发明人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

IPC分类号： H01L21/336 ,  H01L21/337 ,  H01L21/762 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H01L29/80 ,  H01L29/06

CPC分类号： H01L29/66916 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78687 ,  H01L29/802

摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2

摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小 峰值电平朝向未应变硅活性层的表面。 峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。 更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

公开(公告)号：US06914301B2

公开(公告)日：2005-07-05

申请号：US10685116

申请日：2003-10-14

申请人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

发明人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

IPC分类号： H01L21/336 ,  H01L21/337 ,  H01L21/762 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H01L29/80 ,  H01L27/01

CPC分类号： H01L29/66916 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78687 ,  H01L29/802

摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2

摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小 峰值电平朝向未应变硅活性层的表面。 峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。 更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

公开(公告)号：US06878580B2

公开(公告)日：2005-04-12

申请号：US10341563

申请日：2003-01-13

申请人： Geum-jong Bae ,  Nae-in Lee ,  Ki-chul Kim ,  Hwa-sung Rhee ,  Sang-su Kim ,  Jung-il Lee

发明人： Geum-jong Bae ,  Nae-in Lee ,  Ki-chul Kim ,  Hwa-sung Rhee ,  Sang-su Kim ,  Jung-il Lee

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L21/26586 ,  H01L21/2807 ,  H01L21/28114 ,  H01L29/42376

摘要： A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.

摘要翻译： 一种具有负斜率栅极的半导体器件及其制造方法。 形成具有从栅极底部向栅极顶部线性减小的Ge密度分布的多晶硅层，并且通过对多晶硅层进行构图来形成具有负斜率的多晶硅栅极。 通过在图案化时利用Ge密度的蚀刻特性的变化，可以形成底部短于通过光刻限定的顶部的栅极。 因此，门对于短通道器件足够紧凑，并且可以减小栅极电阻。