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    Three-dimensional semiconductor devices
    3.
    发明授权
    Three-dimensional semiconductor devices 有权
    三维半导体器件

    公开(公告)号：US08872183B2

    公开(公告)日：2014-10-28

    申请号：US13366057

    申请日：2012-02-03

    申请人： Sung-Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

    发明人： Sung-Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

    IPC分类号： H01L29/04 ,  H01L21/822 ,  H01L27/115 ,  H01L27/06

    CPC分类号： H01L27/11582 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556 ,  H01L29/4232 ,  H01L29/42372

    摘要： Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

    摘要翻译： 提供三维半导体器件。 三维半导体器件包括衬底，衬底上的缓冲层。 缓冲层包括具有相对于衬底的蚀刻选择性的材料。 在与衬底相对的缓冲层上提供包括交替绝缘图案和导电图案的多层堆叠。 一个或多个有源图案分别延伸穿过多层堆叠的交替绝缘图案和导电图案并进入缓冲层。 还讨论了相关的制造方法。

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES
    4.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES 有权
    三维半导体器件

    公开(公告)号：US20120199897A1

    公开(公告)日：2012-08-09

    申请号：US13366057

    申请日：2012-02-03

    申请人： Sung-Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

    发明人： Sung-Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

    IPC分类号： H01L29/78 ,  H01L29/00

    CPC分类号： H01L27/11582 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556 ,  H01L29/4232 ,  H01L29/42372

    摘要： Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

    摘要翻译： 提供三维半导体器件。 三维半导体器件包括衬底，衬底上的缓冲层。 缓冲层包括具有相对于衬底的蚀刻选择性的材料。 在与衬底相对的缓冲层上提供包括交替绝缘图案和导电图案的多层堆叠。 一个或多个有源图案分别延伸穿过多层堆叠的交替绝缘图案和导电图案并进入缓冲层。 还讨论了相关的制造方法。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    6.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权
    三维半导体存储器件

    公开(公告)号：US20140042520A1

    公开(公告)日：2014-02-13

    申请号：US14057380

    申请日：2013-10-18

    申请人： Changhyun Lee ,  Byoungkeun Son ,  Hyejin Cho

    发明人： Changhyun Lee ,  Byoungkeun Son ,  Hyejin Cho

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7926

    摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

    摘要翻译： 三维（3D）非易失性存储器件包括其中具有第二导电类型（例如，P型）的阱区和在该区域上具有第一导电类型（例如，N型）的公共源极区的衬底。 凹部部分（或完全）延伸穿过公共源区域。 衬底上的垂直堆叠的非易失性存储器单元包括间隔开的栅电极的垂直堆叠和垂直有源区，该垂直有源区延伸在间隔开的栅电极的垂直堆叠的侧壁上并在凹槽的侧壁上延伸。 栅极电介质层在相互间隔开的栅电极的垂直叠层和垂直有源区之间延伸。 栅极电介质层可以包括隧道绝缘层，电荷存储层，相对高的带隙势垒介电层和具有相对高的介电强度的阻挡绝缘层的复合材料。

    Three-dimensional semiconductor memory device
    7.
    发明授权
    Three-dimensional semiconductor memory device 有权
    三维半导体存储器件

    公开(公告)号：US08643080B2

    公开(公告)日：2014-02-04

    申请号：US13217416

    申请日：2011-08-25

    申请人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

    发明人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

    IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L21/06 ,  H01L21/336

    CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided are three-dimensional semiconductor devices. The devices may include gap-fill insulating patterns configured to upwardly extend from a substrate and an electrode structure defined by sidewalls of the gap-fill insulating patterns. Vertical structures may be provided between adjacent ones of the gap-fill insulating patterns to penetrate the electrode structure, and the vertical structures may include first and second rows of the vertical structures. A separation pattern may be provided between the first and second rows of vertical structures and include a separation semiconductor layer. The separation pattern extends along a direction parallel to the first and second rows of vertical structures.

    摘要翻译： 提供三维半导体器件。 这些装置可以包括配置成从基板向上延伸的间隙填充绝缘图案和由间隙填充绝缘图案的侧壁限定的电极结构。 可以在相邻的间隙填充绝缘图案之间提供垂直结构以穿透电极结构，并且垂直结构可以包括垂直结构的第一行和第二行。 可以在第一和第二排垂直结构之间提供分离图案，并且包括分离半导体层。 分离图案沿着平行于第一和第二排垂直结构的方向延伸。

    Three-dimensional semiconductor memory device
    9.
    发明授权
    Three-dimensional semiconductor memory device 有权
    三维半导体存储器件

    公开(公告)号：US08829589B2

    公开(公告)日：2014-09-09

    申请号：US13757273

    申请日：2013-02-01

    申请人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

    发明人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

    IPC分类号： H01L29/788 ,  H01L29/04 ,  H01L29/792

    CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

    摘要： A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer.

    摘要翻译： 三维半导体存储器件可以包括从衬底向上延伸的间隙填充绝缘层，由间隙填充绝缘层的侧壁限定的电极结构，设置在相邻的间隙填充绝缘层之间的垂直结构以穿透 电极结构，以及沿间隙填充绝缘层延伸并穿透电极结构的至少一部分的至少一个分离图案。 分离图案可以包括至少一个分离半导体层。

    Nonvolatile memory device and method of forming the same
    10.
    发明授权
    Nonvolatile memory device and method of forming the same 有权
    非易失存储器件及其形成方法

    公开(公告)号：US08581321B2

    公开(公告)日：2013-11-12

    申请号：US13281612

    申请日：2011-10-26

    申请人： Byoungkeun Son ,  Changhyun Lee ,  Jaegoo Lee ,  Kwang Soo Seol ,  Byungkwan You

    发明人： Byoungkeun Son ,  Changhyun Lee ,  Jaegoo Lee ,  Kwang Soo Seol ,  Byungkwan You

    IPC分类号： H01L29/792 ,  H01L29/76

    CPC分类号： H01L29/66833 ,  H01L27/11582 ,  H01L29/7926

    摘要： A nonvolatile memory device and a method of forming the same, the device including a semiconductor substrate; a plurality of gate patterns stacked on the semiconductor substrate; inter-gate dielectric patterns between the gate patterns; active pillars sequentially penetrating the gate patterns and the inter-gate dielectric patterns to contact the semiconductor substrate; and a gate insulating layer between the active pillars and the gate patterns, wherein corners of the gate patterns adjacent to the active pillars are rounded.

    摘要翻译： 非易失性存储器件及其形成方法，所述器件包括半导体衬底; 堆叠在所述半导体衬底上的多个栅极图案; 栅极图案之间的栅极间电介质图案; 依次穿过栅极图案和栅极间电介质图案以接触半导体衬底的有源支柱; 以及在活性柱和栅极图案之间的栅极绝缘层，其中与活性柱相邻的栅极图案的角部是圆形的。