Method of forming shallow trench isolation
    5.
    发明授权
    Method of forming shallow trench isolation 失效
    形成浅沟槽隔离的方法

    公开(公告)号:US06207535B1

    公开(公告)日:2001-03-27

    申请号:US09531903

    申请日:2000-03-20

    IPC分类号: H01L2176

    CPC分类号: H01L21/76224 Y10S148/05

    摘要: A method of fabricating shallow trench isolations (STI) which forms a substrate with a patterned first oxide layer and a patterned silicon nitride layer thereon, so that active regions are defined with openings formed between the active regions. The openings are then over etched to form trenches for fabricating the STI, followed by forming a second oxide layer that conforms to a profile of the trenches. A third oxide layer is globally formed over the second oxide layer, sidewalls of the first oxide layer, and the silicon nitride layer. A thermal process is performed to densify a portion of the third oxide layer, so that a top portion of the third oxide layer is harder than a lower portion of the third oxide layer. The excessive portion of the third oxide layer above the silicon nitride layer is removed by performing chemical mechanical polishing, which planarizes a top surface of the third oxide layer in order to complete the manufacture of the STI.

    摘要翻译: 制造浅沟槽隔离(STI)的方法,其形成具有图案化的第一氧化物层和其上的图案化氮化硅层的衬底,使得有源区域被限定为在有源区域之间形成的开口。 然后将这些开口过蚀刻以形成用于制造STI的沟槽,随后形成符合沟槽轮廓的第二氧化物层。 在第二氧化物层,第一氧化物层的侧壁和氮化硅层上全局形成第三氧化物层。 执行热处理以使第三氧化物层的一部分致密化,使得第三氧化物层的顶部比第三氧化物层的下部更硬。 通过进行化学机械抛光来去除氮化硅层上方的第三氧化物层的过剩部分,其平坦化第三氧化物层的顶表面以完成STI的制造。

    Method for measuring the kink effect of a semiconductor device
    6.
    发明授权
    Method for measuring the kink effect of a semiconductor device 失效
    用于测量半导体器件的扭结效应的方法

    公开(公告)号:US6046601A

    公开(公告)日:2000-04-04

    申请号:US106745

    申请日:1998-06-30

    IPC分类号: G01R31/26

    CPC分类号: G01R31/2621

    摘要: A method for measuring the extent of the kink effect of a transistor is disclosed herein. The aforementioned method includes the following steps. The first, generate a simulated drain current versus a gate voltage according to the transistor. Secondary, generate a drain current versus the gate voltage. Finally, integrate a difference between the simulated drain current and the drain current by the gate voltage.

    摘要翻译: 本文公开了一种用于测量晶体管的扭结效应的程度的方法。 上述方法包括以下步骤。 首先,根据晶体管产生模拟漏极电流与栅极电压的关系。 次级,产生漏极电流与栅极电压。 最后,通过栅极电压将模拟漏极电流和漏极电流之间的差异相结合。