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公开(公告)号:US20100065954A1
公开(公告)日:2010-03-18
申请号:US12621485
申请日:2009-11-18
申请人: Chao-Chun Tu , Yang-Hui Fang
发明人: Chao-Chun Tu , Yang-Hui Fang
IPC分类号: H01L23/52 , H01L23/522
CPC分类号: H01L25/0657 , H01L23/5226 , H01L24/05 , H01L24/45 , H01L25/0655 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48624 , H01L2224/48647 , H01L2224/49175 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2924/00012
摘要: A semiconductor device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a at least one first bond pads formed on a peripheral region of the first semiconductor die, a at least one re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a at least one wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die is disposed over the first semiconductor die, wherein the second semiconductor die has a at least one second bond pads electrically connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a buffer layer.
摘要翻译: 半导体器件包括第一半导体管芯和第二半导体管芯。 第一半导体管芯包括形成在第一半导体管芯的外围区域上的至少一个第一接合焊盘,形成在第一半导体管芯的中心区域上的至少一个再分布层(RDL)焊盘,以及至少一个 将第一接合焊盘和RDL焊盘互连的一条线路。 第二半导体管芯设置在第一半导体管芯上,其中第二半导体管芯具有通过接合线电连接到RDL焊盘的至少一个第二接合焊盘; 其中所述RDL焊盘由至少缓冲层支持。
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公开(公告)号:US07915744B2
公开(公告)日:2011-03-29
申请号:US12621485
申请日:2009-11-18
申请人: Chao-Chun Tu , Yang-Hui Fang
发明人: Chao-Chun Tu , Yang-Hui Fang
CPC分类号: H01L25/0657 , H01L23/5226 , H01L24/05 , H01L24/45 , H01L25/0655 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48624 , H01L2224/48647 , H01L2224/49175 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2924/00012
摘要: A semiconductor device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a at least one first bond pads formed on a peripheral region of the first semiconductor die, a at least one re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a at least one wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die is disposed over the first semiconductor die, wherein the second semiconductor die has a at least one second bond pads electrically connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a buffer layer.
摘要翻译: 半导体器件包括第一半导体管芯和第二半导体管芯。 第一半导体管芯包括形成在第一半导体管芯的外围区域上的至少一个第一接合焊盘,形成在第一半导体管芯的中心区域上的至少一个再分布层(RDL)焊盘,以及至少一个 将第一接合焊盘和RDL焊盘互连的一条线路。 第二半导体管芯设置在第一半导体管芯上,其中第二半导体管芯具有通过接合线电连接到RDL焊盘的至少一个第二接合焊盘; 其中所述RDL焊盘由至少缓冲层支持。
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公开(公告)号:US07646087B2
公开(公告)日:2010-01-12
申请号:US11855163
申请日:2007-09-14
申请人: Chao-Chun Tu , Yang-Hui Fang
发明人: Chao-Chun Tu , Yang-Hui Fang
CPC分类号: H01L24/05 , H01L23/525 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/48145 , H01L2224/48599 , H01L2224/48624 , H01L2224/48724 , H01L2224/49175 , H01L2225/06506 , H01L2225/06527 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要: A semiconductor device includes a first semiconductor die and a second semiconductor die. The first semiconductor includes a plurality of first bond pads formed on a peripheral region of the first semiconductor die, a plurality of re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a plurality of wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die is disposed over the first semiconductor die, wherein the second semiconductor die has a plurality of second bond pads electrically connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a layer of stress-releasing metal disposed directly underneath the RDL pad.
摘要翻译: 半导体器件包括第一半导体管芯和第二半导体管芯。 第一半导体包括形成在第一半导体管芯的外围区域上的多个第一接合焊盘,形成在第一半导体管芯的中心区域上的多个再分布层(RDL)焊盘以及互连的多个引线路径 第一个接合焊盘和RDL焊盘。 第二半导体管芯设置在第一半导体管芯上,其中第二半导体管芯具有通过接合线电连接到RDL焊盘的多个第二接合焊盘; 其中所述RDL焊盘由直接位于所述RDL焊盘下方的至少一层应力释放金属支撑。
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公开(公告)号:US20080001296A1
公开(公告)日:2008-01-03
申请号:US11855163
申请日:2007-09-14
申请人: Chao-Chun Tu , Yang-Hui Fang
发明人: Chao-Chun Tu , Yang-Hui Fang
IPC分类号: H01L23/52
CPC分类号: H01L24/05 , H01L23/525 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05095 , H01L2224/05554 , H01L2224/05624 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/48145 , H01L2224/48599 , H01L2224/48624 , H01L2224/48724 , H01L2224/49175 , H01L2225/06506 , H01L2225/06527 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要: A semiconductor device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a plurality of first bond pads formed on a peripheral region of the first semiconductor die, a plurality of re-distributed layer (RDL) pads formed on a center region of the first semiconductor die, and a plurality of wire routes interconnecting the first bond pads and the RDL pads. The second semiconductor die deposed over the first semiconductor die, wherein the second semiconductor die has a plurality of second bond pads electrical connecting to the RDL pads via bonding wires; wherein the RDL pad is supported by at least a layer of stress-releasing metal disposed directly underneath the RDL pad.
摘要翻译: 半导体器件包括第一半导体管芯和第二半导体管芯。 第一半导体管芯包括形成在第一半导体管芯的周边区域上的多个第一接合焊盘,形成在第一半导体管芯的中心区域上的多个再分布层(RDL)焊盘,以及多个引线路径 互连第一接合焊盘和RDL焊盘。 第二半导体管芯被放置在第一半导体管芯上,其中第二半导体管芯具有通过接合线电连接到RDL焊盘的多个第二接合焊盘; 其中所述RDL焊盘由直接位于所述RDL焊盘下方的至少一层应力释放金属支撑。
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公开(公告)号:US06207535B1
公开(公告)日:2001-03-27
申请号:US09531903
申请日:2000-03-20
申请人: Kan-Yuan Lee , Joe Ko , Yang-Hui Fang , Gary Hong
发明人: Kan-Yuan Lee , Joe Ko , Yang-Hui Fang , Gary Hong
IPC分类号: H01L2176
CPC分类号: H01L21/76224 , Y10S148/05
摘要: A method of fabricating shallow trench isolations (STI) which forms a substrate with a patterned first oxide layer and a patterned silicon nitride layer thereon, so that active regions are defined with openings formed between the active regions. The openings are then over etched to form trenches for fabricating the STI, followed by forming a second oxide layer that conforms to a profile of the trenches. A third oxide layer is globally formed over the second oxide layer, sidewalls of the first oxide layer, and the silicon nitride layer. A thermal process is performed to densify a portion of the third oxide layer, so that a top portion of the third oxide layer is harder than a lower portion of the third oxide layer. The excessive portion of the third oxide layer above the silicon nitride layer is removed by performing chemical mechanical polishing, which planarizes a top surface of the third oxide layer in order to complete the manufacture of the STI.
摘要翻译: 制造浅沟槽隔离(STI)的方法,其形成具有图案化的第一氧化物层和其上的图案化氮化硅层的衬底,使得有源区域被限定为在有源区域之间形成的开口。 然后将这些开口过蚀刻以形成用于制造STI的沟槽,随后形成符合沟槽轮廓的第二氧化物层。 在第二氧化物层,第一氧化物层的侧壁和氮化硅层上全局形成第三氧化物层。 执行热处理以使第三氧化物层的一部分致密化,使得第三氧化物层的顶部比第三氧化物层的下部更硬。 通过进行化学机械抛光来去除氮化硅层上方的第三氧化物层的过剩部分,其平坦化第三氧化物层的顶表面以完成STI的制造。
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公开(公告)号:US6046601A
公开(公告)日:2000-04-04
申请号:US106745
申请日:1998-06-30
申请人: Meng-Lin Yeh , Yang-Hui Fang
发明人: Meng-Lin Yeh , Yang-Hui Fang
IPC分类号: G01R31/26
CPC分类号: G01R31/2621
摘要: A method for measuring the extent of the kink effect of a transistor is disclosed herein. The aforementioned method includes the following steps. The first, generate a simulated drain current versus a gate voltage according to the transistor. Secondary, generate a drain current versus the gate voltage. Finally, integrate a difference between the simulated drain current and the drain current by the gate voltage.
摘要翻译: 本文公开了一种用于测量晶体管的扭结效应的程度的方法。 上述方法包括以下步骤。 首先,根据晶体管产生模拟漏极电流与栅极电压的关系。 次级,产生漏极电流与栅极电压。 最后,通过栅极电压将模拟漏极电流和漏极电流之间的差异相结合。
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