摘要:
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.
摘要:
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. Each CPU has a local memory, separate from the memory modules, and this local memory is of the dynamic type so it must be periodically refreshed. The refresh cycles are interposed at the same point in the instruction stream for each of the three CPUs by counting instruction execution cycles separately in each CPU, and interrupting to do a refresh cycle when a given count is reached. Stall cycles are also counted, and when long periods of stalls occur then more than one refresh cycle is interposed to catch up to the needed refresh schedule.
摘要:
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.
摘要:
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.
摘要:
An actuator system for extending and flexing a joint, including a multi-motor assembly for providing a rotational output, a rotary-to-linear mechanism for converting the rotational output from the multi-motor assembly into an extension and flexion of the joint, and a controller for operating the actuator system in several operational modes. The multi-motor assembly preferably combines power from two different sources, such that the multi-motor assembly can supply larger forces at slower speeds (“Low Gear”) and smaller forces at higher speeds (“High Gear”). The actuator has been specifically designed for extending and flexing a joint (such as an ankle, a knee, an elbow, or a shoulder) of a human. The actuator system may, however, be used to move any suitable object through any suitable movement (linear, rotational, or otherwise).
摘要:
A motor that delivers high force linear motion or high torque rotary motion to a moving element. The motor may include a driving brake, a driver, a holding brake and a flexible moving element. Operation of the motor may involve activating the holding brake, activating the driver to flex the moving element, activating the holding brake to maintain the position of a portion of the moving element, releasing the driving brake, and restoring the moving element to an unflexed position. The elements are arranged to provide linear motion, belt-driven rotary motion, or directly-coupled rotary motion using brakes and drivers arranged in linear or circular fashion. Drivers may be linear or rotary actuators or motors based on electrostatic, piezoelectric, magnetic, or electrostrictive properties. The brakes may be applied through electrostatic forces, magnetic forces, or mechanical gears engaged with a linear or rotary driving mechanism.
摘要:
A high-power electrostatic actuator comprising rotor and stator layers with fault-tolerant electrode structures, a housing to contain the electrodes and dielectric fluid, and electronic circuitry driving a plurality of high-voltage phases. The actuator is constructed from multiple rotor and stator films separated by spacing elements. The electrode structure provides self-alignment for precise assembly. The actuator assembly includes built-in fine-position sensors to allow optimal timing in powering phases, and a coarse position sensor for feedback control. The electrode structure has a large region of linear force to provide low torque-ripple allowing simple high/low voltage pulsing instead of analog high voltage waveforms. Single or double sided flexible circuit manufacturing techniques are used to fabricate the rotor and stator films at low cost.
摘要:
A method for controlling movement using an active powered device including an actuator, joint position sensor, muscle stress sensor, and control system. The device provides primarily muscle support although it is capable of additionally providing joint support (hence the name “active muscle assistance device”). The device is designed for operation in several modes to provide either assistance or resistance to a muscle for the purpose of enhancing mobility, preventing injury, or building muscle strength. The device is designed to operate autonomously or coupled with other like device(s) to provide simultaneous assistance or resistance to multiple muscles.
摘要:
A disk array controller reliably improves performance in RAID configurations without the need for a battery backup. Write completion interrupts are queued until a write cache flush has been performed and are then sent to a host system. States of ranges of disk addresses (activity bins) are stored in nonvolatile storage elements associated with the ranges. The states allow rebuild times to be reduced after power failures and drive failures. A range is in a Changing state if at least one of the addresses is the target of a write operation that has been initiated but not completed. The range is in a Stable state if no addresses are the target of an uncompleted write operation. Two additional states are used to identify ranges of disk addresses that have been zeroed or never been written to. The additional states allow substantial reductions in RAID volume creation times.
摘要:
A disk array controller reliably improves performance in RAID configurations without the need for a battery backup. Write completion interrupts are queued until a write cache flush has been performed and are then sent to a host system. States of ranges of disk addresses (activity bins) are stored in nonvolatile storage elements associated with the ranges. The states allow rebuild times to be reduced after power failures and drive failures. A range is in a Changing state if at least one of the addresses is the target of a write operation that has been initiated but not completed. The range is in a Stable state if no addresses are the target of an uncompleted write operation. Two additional states are used to identify ranges of disk addresses that have been zeroed or never been written to. The additional states allow substantial reductions in RAID volume creation times.