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公开(公告)号：US5693969A
公开(公告)日：1997-12-02
申请号：US398838
申请日：1995-03-06
IPC分类号： H01L21/28 , H01L21/285 , H01L21/338 , H01L29/08 , H01L29/80 , H01L31/0312
CPC分类号： H01L29/66863 , H01L21/2815 , H01L21/28587 , H01L29/0891
摘要： A lateral MESFET (10,20) utilizes a drain (17) and a source (18) damage termination layer to improve the breakdown voltage of the MESFET (10,20). The source (18) and drain (17) damage termination layers are very shallow to prevent interfering with lateral current flow in the channel layer (12). The source (18) and drain (17) damage termination layers are formed by implanting large inert ions using high implant doses and low implantation energies.
摘要翻译： 横向MESFET（10,20）利用漏极（17）和源极（18）损伤端接层来改善MESFET（10,20）的击穿电压。 源极（18）和漏极（17）损坏终端层非常浅，以防止干扰沟道层（12）中的横向电流。 源（18）和漏极（17）损伤终端层通过使用高注入剂量和低注入能量注入大的惰性离子而形成。
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公开(公告)号：US5895260A
公开(公告)日：1999-04-20
申请号：US625606
申请日：1996-03-29
IPC分类号： H01L21/04 , H01L29/872 , H01L21/28
CPC分类号： H01L29/6606 , H01L29/872
摘要： Fabricating a device including a Schottky diode by growing a dielectric film on a SiC substrate structure and forming an ohmic contact on the opposite surface of the substrate structure by depositing a layer of metal and annealing at a temperature above 900.degree. C. Implanting doping material in the substrate structure through spaced apart openings to form high resistivity areas and depositing a dielectric layer on the dielectric film to define a contact opening positioned between the spaced apart high resistivity areas. Annealing the implant at a temperature less than approximately 400.degree. C. to reduce reverse leakage current and depositing metal in the contact opening to form a Schottky contact.
摘要翻译： 通过在SiC衬底结构上生长电介质膜制造包括肖特基二极管的器件，并通过沉积一层金属并在高于900℃的温度退火，在衬底结构的相对表面上形成欧姆接触。将掺杂材料 衬底结构通过间隔开的开口形成高电阻率区域，并在电介质膜上沉积介电层以限定位于间隔开的高电阻率区域之间的接触开口。 在低于约400℃的温度下退火植入物以减少反向漏电流并在接触开口中沉积金属以形成肖特基接触。
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公开(公告)号：US5877047A
公开(公告)日：1999-03-02
申请号：US912221
申请日：1997-08-15
IPC分类号： H01L21/336 , H01L29/24 , H01L29/78 , H01L21/338
CPC分类号： H01L29/1608 , H01L29/66712 , H01L29/7802 , Y10S438/931
摘要： This is a method of fabricating a lateral gate, vertical drift region transistor including a semiconductor substrate having a drain on the reverse surface. A doped semiconductor layer is formed on the substrate and a high resistivity region is formed adjacent the surface of the doped layer so as to define a vertical drift region in the doped layer. A lateral channel is formed on the high resistivity region and the doped layer so as to communicate with the vertical drift region. A source is positioned on the lateral channel spaced laterally from the vertical drift region and a gate is positioned on the lateral channel between the drift region and the source.
摘要翻译： 这是制造横向栅极，垂直漂移区晶体管的方法，该晶体管包括在反面上具有漏极的半导体衬底。 在衬底上形成掺杂半导体层，并且在掺杂层的表面附近形成高电阻率区域，以便在掺杂层中限定垂直漂移区域。 横向通道形成在高电阻率区域和掺杂层上，以便与垂直漂移区域连通。 源极定位在横向通道上，与垂直漂移区域横向隔开，并且栅极位于漂移区域和源极之间的横向通道上。
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公开(公告)号：US5569937A
公开(公告)日：1996-10-29
申请号：US519864
申请日：1995-08-28
IPC分类号： H01L29/06 , H01L29/24 , H01L29/40 , H01L29/78 , H01L31/0312
CPC分类号： H01L29/404 , H01L29/0615 , H01L29/1608 , H01L29/7835
摘要： A lateral silicon carbide transistor (10) utilizes a modulated channel region (18) to form an accumulation region that facilitates a low on-resistance. A doped region of the channel layer forms a channel insert (14) that also lowers the on-resistance of the transistor (10). A damage termination layer (27) is utilized to facilitate providing a high breakdown voltage. Field plates (23,24) also assists in increasing the breakdown voltage and decreasing the on-resistance of the transistor (10).
摘要翻译： 横向碳化硅晶体管（10）利用调制的沟道区（18）形成促进低导通电阻的积聚区。 沟道层的掺杂区域形成还降低晶体管（10）的导通电阻的沟道插入件（14）。 利用破坏终止层（27）来提供高的击穿电压。 场板（23,24）还有助于提高击穿电压并降低晶体管（10）的导通电阻。
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公开(公告)号：US5956578A
公开(公告)日：1999-09-21
申请号：US839226
申请日：1997-04-23
IPC分类号： H01L27/06 , H01L21/332
CPC分类号： H01L27/0605
摘要： A method of fabricating an integrated VFET and Schottky diode including forming a source region on the upper surface of a substrate so as to define a channel. First and second spaced apart gates are formed on opposing sides of the source region so as to abut the channel, thereby forming a channel structure. Schottky metal is positioned on the upper surface of the substrate proximate the channel structure to define a Schottky diode region and form a Schottky diode. A source contact is formed in communication with the source region and the Schottky metal, and a drain contact is formed on the lower surface of the substrate.
摘要翻译： 一种制造集成的VFET和肖特基二极管的方法，包括在衬底的上表面上形成源极区以形成沟道。 第一和第二间隔开的栅极形成在源极区域的相对侧上，以便邻接沟道，从而形成沟道结构。 肖特基金属位于靠近通道结构的衬底的上表面上以限定肖特基二极管区并形成肖特基二极管。 源极接触形成为与源极区域和肖特基金属连通，并且在衬底的下表面上形成漏极接触。
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公开(公告)号：US5612232A
公开(公告)日：1997-03-18
申请号：US625605
申请日：1996-03-29
IPC分类号： H01L21/04 , H01L21/265 , H01L21/20 , H01L21/44
CPC分类号： H01L29/6606
摘要： A method of fabricating a semiconductor device including forming a Schottky contact on the surface of a substrate by patterning a layer of nickel to define a contact and annealing the nickel below approximately 600.degree. C. A trench is etched around the Schottky contact utilizing the Schottky contact as an etch mask and inert ions are implanted in the trench to form a damage region. The trench is passivated with a dielectric layer. An ohmic contact can be formed on the reverse side of the substrate prior to formation of the Schottky contact.
摘要翻译： 一种制造半导体器件的方法，包括通过对镍层进行图案化以形成接触并将镍退火到约600℃以下，在衬底的表面上形成肖特基接触。利用肖特基接触，在肖特基接触周围蚀刻沟槽 作为蚀刻掩模，并且将惰性离子注入到沟槽中以形成损伤区域。 沟槽用介电层钝化。 在形成肖特基接触之前，可以在衬底的背面形成欧姆接触。
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公开(公告)号：US6002148A
公开(公告)日：1999-12-14
申请号：US497569
申请日：1995-06-30
IPC分类号： H01L21/04 , H01L21/28 , H01L29/24 , H01L29/423 , H01L29/812
CPC分类号： H01L29/1608 , H01L21/0445 , H01L21/0495 , H01L21/2815 , H01L29/42316 , H01L29/66068 , Y10S438/931
摘要： A silicon carbide MESFET (10) is formed to have a source (21) and a drain (22) that are self-aligned to a gate (16) of the MESFET (10). The gate (16) is formed to have a T-shaped structure with a gate-to-source spacer (18) and gate-to-drain spacer (19) along each side of a base of the gate (16). The gate (16) is used as a mask for implanting dopants to form the source (21) and drain (22). A laser annealing is performed after the implantation to activate the dopants. Because the laser annealing is a low temperature operation, the gate (16) is not detrimentally affected during the annealing.
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公开(公告)号：US5641695A
公开(公告)日：1997-06-24
申请号：US538063
申请日：1995-10-02
申请人： Karen E. Moore , Charles E. Weitzel
发明人： Karen E. Moore , Charles E. Weitzel
IPC分类号： H01L21/04 , H01L29/24 , H01L29/808 , H01L21/265 , H01L21/20
CPC分类号： H01L29/1608 , H01L29/66068 , H01L29/808 , Y10S438/931 , Y10S438/945
摘要： An implant mask (14) and an etch mask (16) are utilized in forming a silicon carbide JFET (10). A source opening (17) and a drain opening (18) are formed in the masks (14,16). The etch mask (16) is removed, and a source area (19) and a drain area 21 are implanted through the openings (17,18) and source and drain contact (23, 24) are formed. A protective layer (26) is used to form source and drain contacts (23,24). A gate contact (27) is utilized to ensure the gate (28) is self-aligned to the gate contact (27).
摘要翻译： 在形成碳化硅JFET（10）中使用注入掩模（14）和蚀刻掩模（16）。 在所述掩模（14,16）中形成有源极开口（17）和排出开口（18）。 去除蚀刻掩模（16），并且通过开口（17,18）注入源极区域（19）和漏极区域21，并且形成源极和漏极接触（23,24）。 保护层（26）用于形成源极和漏极接触（23,24）。 栅极接触（27）用于确保栅极（28）与栅极接触件（27）自对准。
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9.发明授权
公开(公告)号：US6127272A
公开(公告)日：2000-10-03
申请号：US13271
申请日：1998-01-26
申请人： Charles E. Weitzel , Karen E. Moore
发明人： Charles E. Weitzel , Karen E. Moore
IPC分类号： H01L21/027 , H01L21/301 , H01L21/338
CPC分类号： H01L21/0277
摘要： A method of performing electron beam lithography on high resistivity substrates including forming semiconductor material on a high resistivity substrate and etching the semiconductor material to form mesas with electrically interconnecting bridges between the mesas. Semiconductor devices are formed in the mesas employing electron beam lithography and charges generated by the electron beam lithography are dispersed along the interconnecting bridges thereby preventing charge accumulation on the mesas. The bridges are removed by etching or sawing during die separation.
摘要翻译： 一种在高电阻率衬底上执行电子束光刻的方法，包括在高电阻率衬底上形成半导体材料并蚀刻半导体材料以形成台面之间的电互连桥的台面。 使用电子束光刻在台面形成半导体器件，并且通过电子束光刻产生的电荷沿着互连桥分散，从而防止台面上的电荷积累。 在分离模具期间通过蚀刻或锯切来除去桥。
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公开(公告)号：US5933750A
公开(公告)日：1999-08-03
申请号：US54561
申请日：1998-04-03
IPC分类号： H01L21/762 , H01L21/58
CPC分类号： H01L21/76254 , H01L21/76251 , Y10S438/977
摘要： A method of fabricating a semiconductor device on thinned wide bandgap material including providing a support having a planar surface and a semiconductor substrate. Implanting a layer of ions in the substrate to create a layer of microbubbles defining a thin film having a planar surface and a remaining mass separated by the layer of implanted ions. Intimately contacting the planar surface of the thin film to the planar surface of the support and heating the support and substrate to separate the remaining mass from the thin film. A semiconductor device is formed on the thin film, and the support is thinned.
摘要翻译： 一种在薄的宽带隙材料上制造半导体器件的方法，包括提供具有平坦表面的支撑体和半导体衬底。 在衬底中植入一层离子以产生限定具有平坦表面的薄膜的微泡层和由注入离子层分离的剩余物质。 将薄膜的平坦表面紧密接触支撑体的平面表面，并加热支撑体和基底，以将剩余的质量与薄膜分离。 半导体器件形成在薄膜上，并且支撑体变薄。
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