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公开(公告)号：US06212639B1
公开(公告)日：2001-04-03
申请号：US09342336
申请日：1999-06-29
IPC分类号： H04K100
CPC分类号： G06F21/57 , G06F12/1408 , G06F21/85
摘要： A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.
摘要翻译： 在可编程逻辑器件（PLD）和存储器件之间传送加密配置数据的方法包括在本发明的一部分中。 该方法包括以下步骤。 将存储在存储设备中的加密配置数据发送到PLD。 解密加密的配置数据以生成PLD中的配置数据的副本。 使用配置数据的副本配置PLD。 在一个实施例中，PLD将密钥发送到存储设备。 在另一个实施例中，密钥分别输入到存储设备和PLD中，并且从未在PLD和存储设备之间传送密钥。 在另一个实施例中，键仅输入到PLD中。 密钥用于加密配置数据。
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公开(公告)号：US5815016A
公开(公告)日：1998-09-29
申请号：US665169
申请日：1996-06-14
申请人： Charles R. Erickson
发明人： Charles R. Erickson
CPC分类号： G06F1/10 , H03L7/0812 , H03L7/085
摘要： A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference dock signal or which produces a selected phase relationship to the reference dock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference dock/output clock relationship. In one embodiment both the positive and negative edges of a clock signal are corrected. As another feature, if correction is consistently in the same direction an error flag is generated.
摘要翻译： 受控的延迟路径将选定的延迟插入到时钟分配电路中，以创建等于相对于参考停靠信号的整数个时钟周期的总时钟延迟，或者产生与参考停靠信号的选择的相位关系。 本发明的延迟路径校正在具有宽范围的可能的系统时钟频率或具有时钟信号的可编程路由以及因此具有宽范围的操作延迟的电路中特别有用。 参考时钟信号通过接收参考时钟信号和反馈信号的相位检测器被引导到可选择的受电压控制的延迟元件的范围，并产生一个误差电压，该误差电压调节电压控制的延迟元件以产生输出时钟信号。 可以包括额外的可选择的延迟，其创建偏移选项并且允许选择引导，滞后或同相参考停靠/输出时钟关系。 在一个实施例中，时钟信号的正和负边缘都被校正。 作为另一个特征，如果校正始终在相同的方向上，则产生错误标志。
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3.发明授权
公开(公告)号：US5789938A
公开(公告)日：1998-08-04
申请号：US707545
申请日：1996-09-04
IPC分类号： G11C8/04 , H03K19/177 , H03K7/38
CPC分类号： H03K19/17772 , G11C8/04 , H03K19/1776
摘要： A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.
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公开(公告)号：US5694056A
公开(公告)日：1997-12-02
申请号：US627815
申请日：1996-04-01
IPC分类号： H03K19/177
CPC分类号： H03K19/17704
摘要： A pipeline frame full detection circuit. The present invention is operable within a system that loads configuration data into an integrated circuit (IC) using a serial data stream and transfer mechanism. Configuration data is transferred into the IC in sequential frames of a specified size for a given IC. The first bit of the configuration data contains a frame full indicator. The configuration data is transferred into a shift register circuit and the last bit position(s) of the shift register circuit, in addition to being stored in the shift register circuit, are shifted along a special frame full pipeline to a control unit. The control unit, upon detecting the frame full indicator, asserts a parallel write command that causes the data of the shift register circuit to be parallel transferred to a receiving column of memory. New configuration data can then be serially shifted into the same shift register circuit after a reset signal. By shifting the frame full indicator through a pipeline, the propagation delay required for the frame full indicator to reach the control unit is significantly reduced. It is this propagation delay that limits the transfer rate of the configuration data into the IC. Therefore, the present invention advantageously reduces this limiting factor.
摘要翻译： 一条流水线全检测电路。 本发明可以在使用串行数据流和传送机制将配置数据加载到集成电路（IC）的系统中操作。 对于给定的IC，配置数据以指定大小的连续帧传送到IC。 配置数据的第一位包含一个帧完整指示符。 配置数据被传送到移位寄存器电路中，并且除了存储在移位寄存器电路之外，移位寄存器电路的最后位位置沿特殊帧完整流水线移动到控制单元。 控制单元在检测到帧全指示符时，断言并行写入命令，使得移位寄存器电路的数据被并行地传送到存储器的接收列。 复位信号后，新的配置数据可以被串行移位到相同的移位寄存器电路中。 通过将帧满指示符移动通过流水线，帧全指示器到达控制单元所需的传播延迟显着降低。 正是这种传播延迟将配置数据的传输速率限制在IC中。 因此，本发明有利地减少了这个限制因素。
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5.发明授权
公开(公告)号：US5613099A
公开(公告)日：1997-03-18
申请号：US409109
申请日：1995-03-23
CPC分类号： G06F9/4435
摘要： A system of modifiable group skeletal formatting of persistent objects. The object oriented framework provides abstract classes for persistent object grouping and storage. Abstract classes define the interfaces and allow implementation details to be deferred until runtime. The implementor creates subclasses overriding the abstract methods and implementing specific group skeletal formats. Multiple formats can be defined and object instance variables set to indicate which formatter to use. The defined interfaces and methods allows interchangeable substitution of group formatters.
摘要翻译： 持久性对象的可修改组骨架格式化系统。 面向对象的框架为持久对象分组和存储提供了抽象类。 抽象类定义接口并允许实现细节被延迟到运行时。 实现者创建覆盖抽象方法并实现特定组骨架格式的子类。 可以定义多种格式，并将对象实例变量设置为指示要使用的格式化程序。 定义的接口和方法允许组格式化程序的可互换替换。
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公开(公告)号：US5489858A
公开(公告)日：1996-02-06
申请号：US246048
申请日：1994-05-19
IPC分类号： H03K19/173 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/00
CPC分类号： H03K19/00361
摘要： Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high skew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.
摘要翻译： 当集成电路器件的许多高电容端子同时从一个逻辑状态移动到另一个逻辑状态时，电源或接地电压可能会波动。 特别是在输出缓冲器的全局高阻抗状态释放之后，其中输出信号被被动地驱动到选择的逻辑状态。 为了防止电源和接地电压变化，缓冲器具有用于以慢响应（高偏移）模式操作的装置。 压摆率控制电路响应于高阻抗信号将缓冲器移动到慢响应模式。 当转换速率控制电路接收到结束缓冲器的高阻状态的信号时，对该信号施加延迟，并且在延迟时间允许缓冲器移动到快速响应模式之后。 当高电容端子移动到新的逻辑状态时，慢速缓冲器响应和缓慢的电压变化可以防止许多端子的同时切换响应电源或接地电压的波动。
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7.发明授权公开(公告)号：US07885820B1
公开(公告)日：2011-02-08
申请号：US09909250
申请日：2001-07-19
IPC分类号： G06Q90/00
摘要： Expert system supported interactive product selection and recommendation. The invention assists an agent to interact with a customer and to provide selection and recommendation of available products and/or services that offer a workable solution for the customer. The invention allows for the use of agents of varying skill levels, including relatively low skill level, without suffering deleterious performance. From certain perspectives, an expert system employed using various aspects of the invention allows the agent to provide real time interaction with a customer and to provide a real time recommended solution to that customer. Many traditional approaches dealing in complex industries require that agent's have a high degree of skill and expertise. The invention allows even a novice agent to service a customer's needs without requiring a high skill level or up-front training that is often at the expense of the provider seeking to market its products and/or services.
摘要翻译： 专家系统支持交互式产品选择和推荐。 本发明帮助代理人与客户进行交互，并提供为客户提供可行解决方案的可用产品和/或服务的选择和推荐。 本发明允许使用具有不同技能水平的试剂，包括技能水平较低，而不会产生有害的性能。 从某些角度来看，使用本发明的各个方面的专家系统允许代理人提供与客户的实时交互并为该客户提供实时推荐的解决方案。 处理复杂行业的许多传统方法要求代理人具有高度的技能和专业知识。 本发明甚至允许新手代理服务于客户的需求，而不需要高技能水平或前期训练，这往往是以寻求上市的产品和/或服务为代价的牺牲品。
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公开(公告)号：US07031951B2
公开(公告)日：2006-04-18
申请号：US09909241
申请日：2001-07-19
IPC分类号： G06F17/00
CPC分类号： H04L41/16 , H04L41/00 , H04L41/145
摘要： An expert system adapted dedicated Internet access guidance engine. The invention allows an agent to interact with a customer and to provide selection and recommendation of data network products and/or services for the customer. The invention allows for the use of agents of varying skill levels, including relatively low skill level, without suffering deleterious performance. The dedicated Internet access guidance engine is operable to perform selection and rating of Internet access products and/or services to provide a solution that meets the needs of a customer. The dedicated Internet access guidance engine is operable to select recommended solutions from among a number of potential solutions that may include compatible solutions. The dedicated Internet access guidance engine is one of the underlying engines within the expert system that allows the agent to provide real time interaction with a customer and to provide a real time recommended solution to that customer.
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公开(公告)号：US5990704A
公开(公告)日：1999-11-23
申请号：US942858
申请日：1997-10-02
IPC分类号： H03K19/0175 , H03K19/20
CPC分类号： H03K19/0002 , H03K19/173
摘要： A multi-state input drive structure is provided to forward externally generated high and low input signals, as well as to receive at least a third, internally generated, comparatively weak signal, preferably an oscillating signal, which triggers a third internally forwarded signal when neither of the high and low input signals is received. The inventive circuit drives three internally forwarded output signals from a single external signal source. Since this circuit may be duplicated for every pin on a device for which two cycle delays do not affect performance, availability of a third input state on N inputs allows 3.sup.N input codes as opposed to 2.sup.N for the conventional "high" and "low" levels normally available.
摘要翻译： 提供多状态输入驱动结构以转发外部产生的高和低输入信号，以及接收至少第三，内部产生的相对较弱的信号，优选振荡信号，其触发第三内部转发信号，当两者 接收高低输入信号。 本发明的电路驱动来自单个外部信号源的三个内部转发的输出信号。 由于对于两个周期延迟不影响性能的设备上的每个引脚可能会复制此电路，所以N个输入上的第三个输入状态的可用性允许3N输入代码，而不是常规的“高”和“低”电平的2N 通常可用。
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10.发明授权Structure and method for reading blocks of data from selectable points in a memory device 失效用于从存储器件中的可选点读取数据块的结构和方法
公开(公告)号：US5923614A
公开(公告)日：1999-07-13
申请号：US71144
申请日：1998-04-30
IPC分类号： G11C8/04 , H03K19/177 , G11C8/00 , G06F7/38
CPC分类号： H03K19/17772 , G11C8/04 , H03K19/1776
摘要： A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.
摘要翻译： 提供了自寻址存储器件，其可以从设备中的多于一个初始位置开始提供数据块，并且可以具有在任一方向上读取的选项。 该存储设备可以有效地存储用于配置一个或多个可配置逻辑设备的多个可能具有不同大小的比特流。 可以以任何顺序访问每个存储的比特流。 在一个实施例中，可配置逻辑器件是现场可编程门阵列（“FPGA”）。 在一个实施例中，存储器件是从全零读取或从全部读取的只读存储器（“ROM”）。 在一个实施例中，ROM包括允许级联多个ROM的双向芯片使能链。
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