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    SEMICONDUCTOR DEVICES HAVING DIFFERENT GATE OXIDE THICKNESSES
    1.
    发明申请
    SEMICONDUCTOR DEVICES HAVING DIFFERENT GATE OXIDE THICKNESSES 有权
    具有不同栅极氧化物厚度的半导体器件

    公开(公告)号：US20140001575A1

    公开(公告)日：2014-01-02

    申请号：US13534012

    申请日：2012-06-27

    申请人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

    发明人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

    摘要： A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

    摘要翻译： 制造具有不同厚度栅极氧化物的多个finFET器件的方法。 该方法可以包括在半导体衬底的顶部上，在第一鳍的顶部上并在第二鳍的顶部上沉积第一介电层; 形成第一虚拟栅极堆叠; 形成第二虚拟栅极叠层; 去除对第一和第二栅极氧化物选择性的第一和第二伪栅极; 掩蔽包括第二鳍片的半导体结构的一部分，并且从第一鳍片顶部去除第一栅极氧化物; 以及在所述第一开口内沉积第二电介质层，并且在所述第二开口内，所述第二电介质层位于所述第一散热片的顶部并且邻近所述第一对电介质间隔件的暴露的侧壁，并且在所述第二栅极的顶部 氧化物并且与第二对电介质间隔物的暴露的侧壁相邻。

    CMOS Circuits with High-K Gate Dielectric
    3.
    发明申请
    CMOS Circuits with High-K Gate Dielectric 审中-公开
    具有高K栅介质的CMOS电路

    公开(公告)号：US20080272438A1

    公开(公告)日：2008-11-06

    申请号：US11743589

    申请日：2007-05-02

    申请人： Bruce B. Doris ,  Charlotte DeWan Adams ,  Eduard Albert Cartier ,  Vijay Narayanan

    发明人： Bruce B. Doris ,  Charlotte DeWan Adams ,  Eduard Albert Cartier ,  Vijay Narayanan

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L29/4983 ,  H01L21/28176 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656

    摘要： A CMOS structure is disclosed in which a first type FET contains a liner, which liner has oxide and nitride portions. The nitride portions are forming the edge segments of the liner. These nitride portions are capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a liner without nitride portions. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have their threshold values set independently from one another.

    摘要翻译： 公开了一种CMOS结构，其中第一类型FET包含衬里，该衬垫具有氧化物和氮化物部分。 氮化物部分形成衬套的边缘部分。 这些氮化物部分能够防止氧气到达第一类型FET的高k电介质栅极绝缘体。 CMOS结构的第二种类型的FET器件具有没有氮化物部分的衬垫。 结果，氧暴露能够移动第二类型FET的阈值电压，而不影响第一类型FET的阈值。 本公开还教导了用于制造CMOS结构的方法，其中不同类型的FET器件具有彼此独立设置的其阈值。

    Methods of forming mixed gate CMOS with single poly deposition
    4.
    发明授权
    Methods of forming mixed gate CMOS with single poly deposition 有权
    使用单个聚合物沉积形成混合栅极CMOS的方法

    公开(公告)号：US07741181B2

    公开(公告)日：2010-06-22

    申请号：US11936061

    申请日：2007-11-06

    申请人： Bruce B. Doris ,  Charlotte DeWan Adams ,  Naim Moumen ,  Ying Zhang

    发明人： Bruce B. Doris ,  Charlotte DeWan Adams ,  Naim Moumen ,  Ying Zhang

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/785

    摘要： A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation. In this latter case the oxidized protective material is incorporated into the metal gate stack, which incorporation results in a novel CMOS structure.

    摘要翻译： 公开了一种在同一芯片上制造金属栅极和多晶硅栅极FET器件的方法。 该方法避免了在不同栅极的栅堆叠制造期间使用两个分离的掩模。 通过使用单个掩模，可以实现更紧密的NFET至PFET距离，并简化制造工艺。 在用于制造金属栅极堆叠的毯布设置层之后，再次以毯子形式形成覆盖保护材料层。 块级别掩模用于清除多晶硅栅极器件区域中的栅极绝缘体形成的表面。 在形成用于多晶硅栅极器件的栅极电介质的氧化期间，保护材料防止金属栅极器件区域的损坏。 在氧化之后，以橡皮布方式设置单个公共多晶硅盖，以继续制造栅极堆叠。 保护材料选择为在氧化时易于除去或在氧化时导电。 在后一种情况下，氧化的保护材料被并入到金属栅极堆叠中，其结合形成了新的CMOS结构。

    Mixed gate CMOS with single poly deposition
    5.
    发明申请
    Mixed gate CMOS with single poly deposition 有权
    混合栅极CMOS与单个聚合物沉积

    公开(公告)号：US20090114992A1

    公开(公告)日：2009-05-07

    申请号：US11936061

    申请日：2007-11-06

    申请人： Bruce B. Doris ,  Charlotte DeWan Adams ,  Naim Moumen ,  Ying Zhang

    发明人： Bruce B. Doris ,  Charlotte DeWan Adams ,  Naim Moumen ,  Ying Zhang

    IPC分类号： H01L29/10 ,  H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/785

    摘要： A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation. In this latter case the oxidized protective material is incorporated into the metal gate stack, which incorporation results in a novel CMOS structure.

    摘要翻译： 公开了一种在同一芯片上制造金属栅极和多晶硅栅极FET器件的方法。 该方法避免了在不同栅极的栅堆叠制造期间使用两个分离的掩模。 通过使用单个掩模，可以实现更紧密的NFET至PFET距离，并简化制造工艺。 在用于制造金属栅极堆叠的毯布设置层之后，再次以毯子形式形成覆盖保护材料层。 块级别掩模用于清除多晶硅栅极器件区域中的栅极绝缘体形成的表面。 在形成用于多晶硅栅极器件的栅极电介质的氧化期间，保护材料防止金属栅极器件区域的损坏。 在氧化之后，以橡皮布方式设置单个公共多晶硅盖，以继续制造栅极堆叠。 保护材料选择为在氧化时易于除去或在氧化时导电。 在后一种情况下，氧化的保护材料被并入到金属栅极堆叠中，其结合形成了新的CMOS结构。