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    Methods of forming mixed gate CMOS with single poly deposition
    1.
    发明授权
    Methods of forming mixed gate CMOS with single poly deposition 有权
    使用单个聚合物沉积形成混合栅极CMOS的方法

    公开(公告)号：US07741181B2

    公开(公告)日：2010-06-22

    申请号：US11936061

    申请日：2007-11-06

    申请人： Bruce B. Doris ,  Charlotte DeWan Adams ,  Naim Moumen ,  Ying Zhang

    发明人： Bruce B. Doris ,  Charlotte DeWan Adams ,  Naim Moumen ,  Ying Zhang

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/785

    摘要： A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation. In this latter case the oxidized protective material is incorporated into the metal gate stack, which incorporation results in a novel CMOS structure.

    摘要翻译： 公开了一种在同一芯片上制造金属栅极和多晶硅栅极FET器件的方法。 该方法避免了在不同栅极的栅堆叠制造期间使用两个分离的掩模。 通过使用单个掩模，可以实现更紧密的NFET至PFET距离，并简化制造工艺。 在用于制造金属栅极堆叠的毯布设置层之后，再次以毯子形式形成覆盖保护材料层。 块级别掩模用于清除多晶硅栅极器件区域中的栅极绝缘体形成的表面。 在形成用于多晶硅栅极器件的栅极电介质的氧化期间，保护材料防止金属栅极器件区域的损坏。 在氧化之后，以橡皮布方式设置单个公共多晶硅盖，以继续制造栅极堆叠。 保护材料选择为在氧化时易于除去或在氧化时导电。 在后一种情况下，氧化的保护材料被并入到金属栅极堆叠中，其结合形成了新的CMOS结构。

    Mixed gate CMOS with single poly deposition
    2.
    发明申请
    Mixed gate CMOS with single poly deposition 有权
    混合栅极CMOS与单个聚合物沉积

    公开(公告)号：US20090114992A1

    公开(公告)日：2009-05-07

    申请号：US11936061

    申请日：2007-11-06

    申请人： Bruce B. Doris ,  Charlotte DeWan Adams ,  Naim Moumen ,  Ying Zhang

    发明人： Bruce B. Doris ,  Charlotte DeWan Adams ,  Naim Moumen ,  Ying Zhang

    IPC分类号： H01L29/10 ,  H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/785

    摘要： A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation. In this latter case the oxidized protective material is incorporated into the metal gate stack, which incorporation results in a novel CMOS structure.

    摘要翻译： 公开了一种在同一芯片上制造金属栅极和多晶硅栅极FET器件的方法。 该方法避免了在不同栅极的栅堆叠制造期间使用两个分离的掩模。 通过使用单个掩模，可以实现更紧密的NFET至PFET距离，并简化制造工艺。 在用于制造金属栅极堆叠的毯布设置层之后，再次以毯子形式形成覆盖保护材料层。 块级别掩模用于清除多晶硅栅极器件区域中的栅极绝缘体形成的表面。 在形成用于多晶硅栅极器件的栅极电介质的氧化期间，保护材料防止金属栅极器件区域的损坏。 在氧化之后，以橡皮布方式设置单个公共多晶硅盖，以继续制造栅极堆叠。 保护材料选择为在氧化时易于除去或在氧化时导电。 在后一种情况下，氧化的保护材料被并入到金属栅极堆叠中，其结合形成了新的CMOS结构。

    Semiconductor transistors having high-K gate dielectric layers, metal gate electrode regions, and low fringing capacitances
    4.
    发明授权
    Semiconductor transistors having high-K gate dielectric layers, metal gate electrode regions, and low fringing capacitances 有权
    具有高K栅极电介质层，金属栅电极区域和低边缘电容的半导体晶体管

    公开(公告)号：US08232612B2

    公开(公告)日：2012-07-31

    申请号：US12645981

    申请日：2009-12-23

    申请人： James William Adkisson ,  Michael P. Chudzik ,  Jeffrey Peter Gambino ,  Renee T. Mo ,  Naim Moumen

    发明人： James William Adkisson ,  Michael P. Chudzik ,  Jeffrey Peter Gambino ,  Renee T. Mo ,  Naim Moumen

    IPC分类号： H01L21/00

    CPC分类号： H01L29/4983 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S257/90

    摘要： A semiconductor structure. The structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a gate dielectric region, and (iv) a gate electrode region, (v) a plurality of interconnect layers on the gate electrode region, and (vi) first and second spaces. The gate dielectric region is disposed between and in direct physical contact with the channel region and the gate electrode region. The gate electrode region is disposed between and in direct physical contact with the gate dielectric region and the interconnect layers. The first and second spaces are in direct physical contact with the gate electrode region. The first space is disposed between the first source/drain region and the gate electrode region. The second space is disposed between the second source/drain region and the gate electrode region.

    摘要翻译： 半导体结构。 该结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）栅极电介质区，和（iv）栅电极区，（v） 栅电极区上的多个互连层，以及（vi）第一和第二空间。 栅极电介质区域设置在沟道区域和栅电极区域之间并与其直接物理接触。 栅电极区域设置在栅极电介质区域和互连层之间并与其直接物理接触。 第一和第二空间与栅电极区域直接物理接触。 第一空间设置在第一源极/漏极区域和栅极电极区域之间。 第二空间设置在第二源极/漏极区域和栅极电极区域之间。

    Gate Effective-Workfunction Modification for CMOS
    5.
    发明申请
    Gate Effective-Workfunction Modification for CMOS 有权
    门有效功能修改CMOS

    公开(公告)号：US20110121401A1

    公开(公告)日：2011-05-26

    申请号：US13019949

    申请日：2011-02-02

    申请人： Dae-Gyu Park ,  Michael P. Chudzik ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Dae-Gyu Park ,  Michael P. Chudzik ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Naim Moumen ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/785

    摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

    摘要翻译： 公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。 在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。 还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

    Disposable metallic or semiconductor gate spacer
    6.
    发明授权
    Disposable metallic or semiconductor gate spacer 失效
    一次性金属或半导体栅极间隔物

    公开(公告)号：US07682917B2

    公开(公告)日：2010-03-23

    申请号：US12016326

    申请日：2008-01-18

    申请人： Stephen W. Bedell ,  Michael Chudzik ,  William K. Henson ,  Naim Moumen ,  Vijay Narayanan ,  Devendra K. Sadana ,  Kathryn T. Schonenberg ,  Ghavam Shahidi

    发明人： Stephen W. Bedell ,  Michael Chudzik ,  William K. Henson ,  Naim Moumen ,  Vijay Narayanan ,  Devendra K. Sadana ,  Kathryn T. Schonenberg ,  Ghavam Shahidi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7847 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

    摘要： A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as a metal, a metal nitride, or a semiconductor material having high reactivity with oxygen. The disposable gate spacer absorbs any oxygen during subsequent high temperature processing such as a stress memorization anneal. A metal is deposited over, and reacted with, the gate electrode and source and drain regions to form metal semiconductor alloy regions. The disposable gate spacer is subsequently removed selective to the metal semiconductor alloy regions. A porous or non-porous low-k dielectric material is deposited to provide a low parasitic capacitance between the gate electrode and the source and drain regions. The gate dielectric maintains the original dielectric constant since the disposable gate spacer prevents absorption of additional oxygen during high temperature processes.

    摘要翻译： 一次性间隔物直接形成在栅极电极和栅极电介质的侧壁上或紧邻栅电极的侧壁上。 一次性间隔件包括清除氧的材料，例如金属，金属氮化物或具有高氧反应性的半导体材料。 一次性栅极间隔件在随后的高温处理例如应力记忆退火期间吸收任何氧气。 将金属沉积在栅电极和源极和漏极区上并与其反应以形成金属半导体合金区域。 一次性栅极间隔物随后被选择性地移除到金属半导体合金区域。 沉积多孔或非多孔低k电介质材料以在栅极电极和源极和漏极区域之间提供低的寄生电容。 栅极电介质保持原始介电常数，因为一次性栅极间隔物可防止在高温过程中吸收额外的氧。

    Immersion optical lithography system having protective optical coating
    7.
    发明申请
    Immersion optical lithography system having protective optical coating 有权
    具有保护性光学涂层的浸没光学光刻系统

    公开(公告)号：US20080225251A1

    公开(公告)日：2008-09-18

    申请号：US12154003

    申请日：2008-05-19

    申请人： Steven J. Holmes ,  Toshiharu Furukawa ,  Charles W. Koburger ,  Naim Moumen

    发明人： Steven J. Holmes ,  Toshiharu Furukawa ,  Charles W. Koburger ,  Naim Moumen

    IPC分类号： G03B27/52

    CPC分类号： G03F7/2041 ,  G03F7/11 ,  G03F7/70341 ,  G03F7/70958

    摘要： An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

    摘要翻译： 提供了一种浸没光刻系统，其包括可操作以产生具有标称波长的光和光学成像系统的光源。 光学成像系统具有从光源到待图案化的制品的光路中的光学元件。 光学元件具有适于接触占据面部和制品之间的空间的液体的面。 光学元件包括可被液体降解的材料和覆盖面上的可降解材料以保护面部免受液体的保护涂层，保护涂层对于光是透明的，当暴露于光时稳定，并且当稳定时 暴露于液体。

    IMMERSION OPTICAL LITHOGRAPHY SYSTEM HAVING PROTECTIVE OPTICAL COATING
    8.
    发明申请
    IMMERSION OPTICAL LITHOGRAPHY SYSTEM HAVING PROTECTIVE OPTICAL COATING 失效
    具有保护光学涂层的光学光刻系统

    公开(公告)号：US20070076179A1

    公开(公告)日：2007-04-05

    申请号：US11163007

    申请日：2005-09-30

    申请人： Steven Holmes ,  Toshiharu Furukawa ,  Charles Koburger III ,  Naim Moumen

    发明人： Steven Holmes ,  Toshiharu Furukawa ,  Charles Koburger III ,  Naim Moumen

    IPC分类号： G03B27/42

    CPC分类号： G03F7/2041 ,  G03F7/11 ,  G03F7/70341 ,  G03F7/70958

    摘要： An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

    摘要翻译： 提供了一种浸没光刻系统，其包括可操作以产生具有标称波长的光和光学成像系统的光源。 光学成像系统具有从光源到待图案化的制品的光路中的光学元件。 光学元件具有适于接触占据面部和制品之间的空间的液体的面。 光学元件包括可被液体降解的材料和覆盖面上的可降解材料以保护面部免受液体的保护涂层，保护涂层对于光是透明的，当暴露于光时稳定，并且当稳定时 暴露于液体。

    Air gaps between conductive lines for reduced RC delay of integrated circuits
    9.
    发明授权
    Air gaps between conductive lines for reduced RC delay of integrated circuits 有权
    导线之间的气隙用于减少集成电路的RC延迟

    公开(公告)号：US07125782B2

    公开(公告)日：2006-10-24

    申请号：US10965370

    申请日：2004-10-14

    申请人： Andreas Knorr ,  Bernd Kastenmeier ,  Naim Moumen

    发明人： Andreas Knorr ,  Bernd Kastenmeier ,  Naim Moumen

    IPC分类号： H01L21/764

    CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming air gaps or porous dielectric materials between interconnects of integrated circuits and structures thereof. Air gaps or highly porous dielectric material having a dielectric constant of close to or equal to 1.0 are formed in a first region but not a second region of an interconnect layer. The air gaps or highly porous dielectric material are formed by depositing a first insulating material comprising an energy-sensitive material over a workpiece, depositing a second insulating material over the first insulating material, and exposing the workpiece to energy. At least a portion of the first insulating material in the first region is removed through the second insulating material. Structurally stable insulating material is disposed between conductive lines in the second region of the workpiece, providing mechanical strength for the integrated circuit.

    摘要翻译： 在集成电路的互连和其结构之间形成气隙或多孔电介质材料的方法。 介电常数接近或等于1.0的气隙或高度多孔介电材料形成在互连层的第一区域而不是第二区域中。 通过在工件上沉积包含能量敏感材料的第一绝缘材料，在第一绝缘材料上沉积第二绝缘材料，并将工件暴露于能量来形成气隙或高度多孔介电材料。 通过第二绝缘材料去除第一区域中的第一绝缘材料的至少一部分。 结构上稳定的绝缘材料设置在工件的第二区域中的导线之间，为集成电路提供机械强度。

    Collar formation using selective SiGe/Si etch
    10.
    发明授权
    Collar formation using selective SiGe/Si etch 失效
    使用选择性SiGe / Si蚀刻的环形结构

    公开(公告)号：US06924205B2

    公开(公告)日：2005-08-02

    申请号：US10770278

    申请日：2004-02-02

    申请人： Naim Moumen

    发明人： Naim Moumen

    IPC分类号： H01L27/108 ,  H01L21/306 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/20

    CPC分类号： H01L27/1087 ,  H01L21/30604 ,  H01L29/66181 ,  H01L29/945

    摘要： A method of forming collar isolation for a trench storage memory cell structure is provided in which amorphous Si (a:Si) and silicon germanium (SiGe) are first formed into a trench structure. An etching process that is selective to a:Si as compared to SiGe is employed in defining the regions in which the collar isolation will be formed. The selective etching process employed in the present invention is a wet etch process that includes etching with HF, rinsing, etching with NH4OH, rinsing, and drying with a monohydric alcohol such as isopropanol. The sequence of NH4OH etching and rinsing may be repeated any number of times. The conditions used in the selective etching process of the present invention are capable of etching a:Si at a faster rate than SiGe.

    摘要翻译： 提供了一种形成沟槽存储单元结构的套环隔离的方法，其中首先将非晶硅（a：Si）和硅锗（SiGe）形成沟槽结构。 与SiGe相比，对a：Si有选择性的蚀刻工艺用于限定将形成套环隔离的区域。 在本发明中采用的选择性蚀刻方法是湿式蚀刻工艺，其包括用HF蚀刻，漂洗，用NH 4 OH蚀刻，漂洗和用一元醇如异丙醇干燥。 NH 4 OH蚀刻和漂洗的顺序可以重复任意次数。 在本发明的选择性蚀刻工艺中使用的条件能够以比SiGe更快的速度蚀刻Si。