公开(公告)号：US06933567B2

公开(公告)日：2005-08-23

申请号：US10146158

申请日：2002-05-15

申请人： Charvaka Duvvury ,  Sridhar Ramaswamy

发明人： Charvaka Duvvury ,  Sridhar Ramaswamy

IPC分类号： H01L23/62 ,  H01L27/02 ,  H01L31/392

CPC分类号： H01L27/0277

摘要： An electrostatic discharge (ESD) protection device formed in the semiconductor layer of a semiconductor-on-insulator device, wherein the semiconductor layer has first and second wells. A discharge circuit is formed in the first well, operable to discharge the ESD pulse to ground. A pump circuit is formed in the second well, operable to use a portion of an ESD pulse's voltage to pump current into the first well for allowing the discharge circuit to turn on uniformly. The discharge circuit has a plurality of body nodes to the first well. The pump circuit comprises an input pad for receiving a portion of the ESD pulse's voltage; an MOS transistor having source, gate and drain; a capacitor connected between the input pad and the gate, whereby a rising input voltage pulls the gate transiently high for pumping current into the first well; the source is connected to the body nodes of the discharge circuit, and the drain connected to the input pad.

摘要翻译： 一种形成在绝缘体上半导体器件的半导体层中的静电放电（ESD）保护器件，其中半导体层具有第一和第二阱。 在第一阱中形成放电电路，用于将ESD脉冲放电到地。 泵电路形成在第二阱中，可操作以使用ESD脉冲的一部分电压将电流泵入第一阱，以允许放电电路均匀地导通。 放电电路具有到第一阱的多个体节点。 泵电路包括用于接收ESD脉冲电压的一部分的输入焊盘; 具有源极，栅极和漏极的MOS晶体管; 连接在输入焊盘和栅极之间的电容器，由此上升的输入电压将栅极瞬时拉高以将电流泵入第一阱; 源极连接到放电电路的主体节点，并且漏极连接到输入焊盘。

公开(公告)号：US6040968A

公开(公告)日：2000-03-21

申请号：US99654

申请日：1998-06-17

申请人： Charvaka Duvvury ,  E. Ajith Amerasekera ,  Sridhar Ramaswamy

发明人： Charvaka Duvvury ,  E. Ajith Amerasekera ,  Sridhar Ramaswamy

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0251 ,  H01L27/0248

摘要： A method for achieving improving ESD protection in integrated circuits. Capacitance associated with a power supply plays an important role in ESD protection and increasing Vcc.sub.-- c capacitance by integrating distributed capacitors as junction capacitors, or MOS capacitors along Vcc and grounded n+ diffusion parallel runs improves protection against ESD and EOS. Additionally, at least a pair of antiparallel diodes interposed between the periphery voltage source and internal core circuitry voltage provides an added noise margin.

摘要翻译： 实现集成电路中ESD保护改进的方法。 与电源相关的电容在ESD保护中起着重要作用，通过将分布式电容器集成为结电容器，或沿着Vcc和接地的n +扩散并联运行的MOS电容器提高Vcc-c电容，提高了ESD和EOS的保护。 此外，插入在外围电压源和内部电路电压之间的至少一对反并联二极管提供了增加的噪声容限。

公开(公告)号：US5796638A

公开(公告)日：1998-08-18

申请号：US668856

申请日：1996-06-24

申请人： Sung-Mo Steve Kang ,  Charvaka Duvvury ,  Carlos Hernando Diaz ,  Sridhar Ramaswamy

发明人： Sung-Mo Steve Kang ,  Charvaka Duvvury ,  Carlos Hernando Diaz ,  Sridhar Ramaswamy

IPC分类号： G06F17/50 ,  H01L27/02

CPC分类号： G06F17/5068 ,  H01L27/0248

摘要： A method, apparatus and computer program product for synthesizing and correcting ESD and EOS ground rules faults in integrated circuits generates a representation of a first functional circuit element (e.g., logic gate) connected to a representation of a first input/output (I/O) pad, via a representation of a first electrical path, and generates a representation of a first ESD circuit element connected to the representation of the first input/output pad via a representation of a second electrical path which may overlap a portion of the first electrical path. First and second sheet resistances (or quantities related thereto) of the first and second electrical paths, respectively, are determined and a length and/or width of the representation of at least one of the first and second electrical paths is adjusted if the first sheet resistance is greater than the second sheet resistance, so that the first sheet resistance is less than the second sheet resistance. Corners in representations of adjacent power rails are also detected, where these representations have opposing edges separated by a minimum rail spacing, and a position of at least one of the power rails relative to the other is adjusted so that the opposing edges are separated by a spacing which is no less than about two times the minimum rail spacing.

摘要翻译： 用于在集成电路中合成和校正ESD和EOS接地规则故障的方法，装置和计算机程序产品产生连接到第一输入/输出（I / O）的表示的第一功能电路元件（例如，逻辑门）的表示 ）焊盘，经由第一电路径的表示，并且经由第二电路径的表示产生连接到第一输入/输出焊盘的表示的第一ESD电路元件的表示，该第二电路径可以与第一电路的一部分重叠 路径。 确定第一和第二电路径的第一和第二薄片电阻（或相关数量），并且如果第一薄片和第二电路径的第一和第二电路径的至少之一的表示的长度和/或宽度被调整， 电阻大于第二薄层电阻，使得第一薄层电阻小于第二薄层电阻。 还检测到相邻电力轨道表示的角，其中这些表示具有由最小轨道间隔分开的相对边缘，并且调节至少一个电力轨道相对于另一个的位置，使得相对边缘由 间距不小于最小轨道间距的大约两倍。

公开(公告)号：US06667865B2

公开(公告)日：2003-12-23

申请号：US09864506

申请日：2001-05-24

申请人： Charvaka Duvvury ,  Sridhar Ramaswamy

发明人： Charvaka Duvvury ,  Sridhar Ramaswamy

IPC分类号： H02H900

CPC分类号： H01L27/0288 ,  H01L27/0266

摘要： A semiconductor device is designed with a common supply voltage terminal (330). A plurality of standard cells (360-364), each having a plurality of leads (308,326) is connected to the common supply terminal. A plurality of connecting leads (322-324) corresponding to respective standard cells is coupled between at least two leads of the plurality of leads.

摘要翻译： 半导体器件设计有公共电源电压端子（330）。 多个具有多个引线（308,326）的标准单元（360-364）连接到公共供电端子。 对应于各个标准单元的多个连接引线（322-324）耦合在多个引线的至少两个引线之间。

公开(公告)号：US06493850B2

公开(公告)日：2002-12-10

申请号：US09785706

申请日：2001-02-16

申请人： Puvvada Venugopal ,  Snehamay Sinha ,  Sridhar Ramaswamy ,  Charvaka Duvvury ,  Guru C. Prasad ,  C. S. Raghu ,  Gopalaro Kadamati

发明人： Puvvada Venugopal ,  Snehamay Sinha ,  Sridhar Ramaswamy ,  Charvaka Duvvury ,  Guru C. Prasad ,  C. S. Raghu ,  Gopalaro Kadamati

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.

摘要翻译： 为了定量识别集成电路（IC）设计中的静电放电（ESD）和闩锁的灵敏度（在实际的IC制造之前），所公开的计算机系统和方法将来自设计网表，元件模型，安全 操作文件和压力模拟列表，并将模拟量化的ESD事件应用于设计。 然后定量分析设计元件对ESD和闭锁的观察灵敏度，判断临界应力值，记录元件故障。 最后，灵敏度和故障的元素和位置列表以特定格式输出。

公开(公告)号：US08818856B2

公开(公告)日：2014-08-26

申请号：US13285856

申请日：2011-10-31

申请人： Leslie Yeh ,  Sridhar Ramaswamy ,  Zhe Qian ,  Mark Rose

发明人： Leslie Yeh ,  Sridhar Ramaswamy ,  Zhe Qian ,  Mark Rose

IPC分类号： G06F17/30

CPC分类号： G06Q30/0257 ,  G06F17/3087 ,  G06Q30/02 ,  G06Q30/0205 ,  G06Q30/0242 ,  G06Q30/0244 ,  G06Q30/0246 ,  G06Q30/0254 ,  G06Q30/0261

摘要： The usefulness, and consequently the performance, of advertisements are improved by allowing businesses to better target their ads to a responsive audience. For example, location information may be used in ad relevancy determination, and in attribute (e.g., position) arbitration. Such location information may be associated with price information, such as a maximum price bid, and/or with ad performance information. Ad performance information may be tracked on the basis of location information. The content of an ad creative, and/or of a landing page may be selected and/or modified using location information. Tools may be provided to enter and/or modify location information, such as location-dependent targeting information and price information. The location information used to target and/or score ads may be, include, or define an area. The area may be defined by at least one geographic reference point (e.g., defined by latitude and longitude coordinates) and perhaps additional information.

摘要翻译： 通过允许企业更好地将广告定位到敏感的受众群体，改善了广告的有用性以及性能。 例如，可以在广告相关性确定和属性（例如，位置）仲裁中使用位置信息。 这样的位置信息可以与价格信息（例如最大价格出价）和/或与广告效果信息相关联。 可以基于位置信息跟踪广告效果信息。 可以使用位置信息来选择和/或修改广告素材的内容和/或着陆页的内容。 可以提供工具来输入和/或修改位置信息，例如与位置相关的目标信息和价格信息。 用于定位和/或评分广告的位置信息可以是，包括或定义一个区域。 该区域可以由至少一个地理参考点（例如，由纬度和经度坐标定义）和可能的附加信息来定义。

公开(公告)号：US08412575B2

公开(公告)日：2013-04-02

申请号：US11172614

申请日：2005-06-30

申请人： Wilburt Labio ,  Sridhar Ramaswamy ,  Mark Rose

发明人： Wilburt Labio ,  Sridhar Ramaswamy ,  Mark Rose

IPC分类号： G06Q30/00

CPC分类号： G06Q30/08 ,  G06Q30/02 ,  G06Q30/0247 ,  G06Q30/0249 ,  G06Q30/0256

摘要： Offers, such as bids in an advertising network, may be determined and/or managed by accepting an ad budget and at least one ad serving constraint, and then generating offer information using the ad budget and the serving constraint(s). The offer may be generated by obtaining, for each of the ad serving constraint(s), a plurality of points, wherein each point includes a cost per event value and an event quantity value. These points collectively define a landscape. A convex landscape for each of the ad serving constraint(s) is then determined from the landscape(s). One or more points from at least one of the convex landscapes is then used to generate the offer information.

摘要翻译： 可以通过接受广告预算和至少一个广告投放约束来确定和/或管理诸如广告网络中的出价的优惠，然后使用广告预算和服务约束生成报价信息。 可以通过为每个广告服务约束获得多个点来生成报价，其中每个点包括每个事件值的成本和事件数量值。 这些点共同定义了一个景观。 然后从景观确定每个广告服务约束的凸面景观。 然后使用至少一个凸形景观的一个或多个点来产生报价信息。

公开(公告)号：US07173498B2

公开(公告)日：2007-02-06

申请号：US10952343

申请日：2004-09-28

申请人： Sridhar Ramaswamy ,  Hassan O. Ali ,  Song Wu

发明人： Sridhar Ramaswamy ,  Hassan O. Ali ,  Song Wu

IPC分类号： H03B5/12 ,  H03B1/04 ,  H03B5/08 ,  H01L29/41

CPC分类号： H01L27/0207 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/552 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/3025 ,  H03L7/099 ,  H01L2224/0401

摘要： Disclosed are integrated circuits having multiple electromagnetically emissive devices, such as LC oscillators. The devices are formed on an integrated circuit substrate and are given different planar orientations from each other. Particular integrated circuit packages disclosed are “flip-chip” packages, in which solder bumps are provided on the integrated circuit substrate for flipping and mounting of the finished integrated circuit upon a printed circuit board or other substrate. The solder bumps provide conductive connections between the integrated circuit and the substrate. The orientations and positioning of the emissive devices are such that one or more of the solder bumps are interposed between neighboring emissive devices to act as an electromagnetic shield between them.

摘要翻译： 公开了具有多个电磁放射器件的集成电路，例如LC振荡器。 这些器件形成在集成电路衬底上并且被赋予彼此不同的平面取向。 公开的具体的集成电路封装是“倒装芯片”封装，其中在集成电路基板上提供焊料凸块以便将成品集成电路翻转和安装在印刷电路板或其它基板上。 焊料凸块提供集成电路和衬底之间的导电连接。 发射装置的取向和定位使得一个或多个焊料凸块插入在相邻发射装置之间以用作它们之间的电磁屏蔽。

公开(公告)号：US20050182807A1

公开(公告)日：2005-08-18

申请号：US10777238

申请日：2004-02-12

申请人： Sridhar Ramaswamy ,  Song Wu ,  Bhavesh Bhakta

发明人： Sridhar Ramaswamy ,  Song Wu ,  Bhavesh Bhakta

IPC分类号： G06F17/15 ,  H04L1/20 ,  H04L1/24 ,  H04L25/02

CPC分类号： H04L1/24 ,  H04L1/203 ,  H04L25/0212

摘要： A method, and associated storage medium containing software and a system, comprises extracting a time domain impulse response from parameters that characterize a communication channel, generating a probability distribution function (PDF) of an output voltage based on the impulse response; and computing a relationship between bit error rate and voltage margin based on the final probability distribution function. Generating the PDF of the output voltage may comprise one or more of the following acts: quantizing the impulse response into a plurality of quantized levels, assigning taps to the quantized levels and determining a number of taps assigned to each quantized level, determining allowable voltage levels for each quantized level, and determining a probability of occurrence of each allowable voltage level, determining a PDF for each voltage level; and convolving all of the PDFs for the various voltage levels to obtain the PDF of the output voltage.

摘要翻译： 一种包含软件和系统的方法和相关联的存储介质，包括从表征通信信道的参数中提取时域脉冲响应，基于脉冲响应产生输出电压的概率分布函数（PDF）; 并基于最终概率分布函数计算误码率和电压余量之间的关系。 生成输出电压的PDF可以包括以下动作中的一个或多个：将脉冲响应量化为多个量化电平，为量化电平分配抽头并且确定分配给每个量化电平的抽头数量，确定容许电压电平 并且确定每个可允许电压电平的发生概率，确定每个电压电平的PDF; 并卷积所有PDF的各种电压电平，以获得输出电压的PDF。

公开(公告)号：US20050180498A1

公开(公告)日：2005-08-18

申请号：US10777612

申请日：2004-02-12

申请人： Bhavesh Bhakta ,  Sridhar Ramaswamy ,  Robert Payne ,  Song Wu

发明人： Bhavesh Bhakta ,  Sridhar Ramaswamy ,  Robert Payne ,  Song Wu

IPC分类号： H03H21/00 ,  H03K5/159 ,  H04L25/03

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

摘要： An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signals from the sampler and generates equalization signals therefrom. The summer couples to the sampler and the filter and combines together the input communication signal with the equalization signals. Further, a plurality of clocks control timing associated with the sampler. These clocks have frequencies that are less than the predetermined data rate of the digital decision output signals.

摘要翻译： 均衡器包括采样器，滤波器和夏季。 采样器采样表示输入通信信号的信号，以确定具有通信设备数据速率的数字判定输出信号。 滤波器从采样器接收数字判定输出信号，并从中产生均衡信号。 夏天耦合到采样器和滤波器，并将输入通信信号与均衡信号组合在一起。 此外，多个时钟控制与采样器相关联的定时。 这些时钟具有小于数字决策输出信号的预定数据速率的频率。