公开(公告)号：US12191226B2

公开(公告)日：2025-01-07

申请号：US18155322

申请日：2023-01-17

Applicant: MEDIATEK INC. ,  Chee-Wee Liu

Inventor： Ming-Tzong Yang ,  Hsien-Hsin Lin ,  Wen-Kai Wan ,  Chia-Che Chung ,  Chee-Wee Liu

IPC: H01L23/373 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm−1K−1 and 1200 Wm−1K−1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate.

公开(公告)号：US11587846B2

公开(公告)日：2023-02-21

申请号：US17133896

申请日：2020-12-24

Applicant: MEDIATEK INC. ,  Chee-Wee Liu

Inventor： Ming-Tzong Yang ,  Hsien-Hsin Lin ,  Wen-Kai Wan ,  Chia-Che Chung ,  Chee-Wee Liu

IPC: H01L23/373 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm−1K−1 and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor. A method of forming a semiconductor device includes providing a base substrate, forming a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is greater than 200 Wm−1K−1. The method further includes forming a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further includes removing the base substrate.

公开(公告)号：US20220059429A1

公开(公告)日：2022-02-24

申请号：US17133896

申请日：2020-12-24

Applicant: Chee-Wee LIU ,  MEDIATEK INC.

Inventor： Ming-Tzong Yang ,  Hsien-Hsin Lin ,  Wen-Kai Wan ,  Chia-Che Chung ,  Chee-Wee Liu

IPC: H01L23/373 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm−1K−1and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor.

公开(公告)号：US20130087191A1

公开(公告)日：2013-04-11

申请号：US13341526

申请日：2011-12-30

Applicant: Seow-Wei TAN ,  Yen-Yu Chen ,  Wei-Shuo Ho ,  Yu-Hung Huang ,  Chee-Wee Liu

Inventor： Seow-Wei TAN ,  Yen-Yu Chen ,  Wei-Shuo Ho ,  Yu-Hung Huang ,  Chee-Wee Liu

IPC: H01L31/0224 ,  H01L31/0216

CPC classification number: H01L31/022425 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A point-contact solar cell structure includes a semiconductor substrate, a front electrode, a first passivation layer, a second passivation layer, and a rear electrode. The semiconductor substrate includes an upper surface, a lower surface, and an emitter layer, a base layer, and a plurality of locally doped regions located between the upper surface and the lower surface. The plurality of locally doped regions is located on the lower surface at intervals. The second passivation layer is located on the lower surface, and has a plurality of openings disposed respectively corresponding to the locally doped regions. The rear electrode is located on one side of the second passivation layer opposite to the semiconductor substrate, and passes through the second passivation layer via the openings to contact the locally doped regions. The width of at least one opening corresponding to the front electrode is greater than that of the remaining openings.

Abstract translation: 点接触太阳能电池结构包括半导体衬底，前电极，第一钝化层，第二钝化层和后电极。 半导体衬底包括位于上表面和下表面之间的上表面，下表面和发射极层，基底层和多个局部掺杂区域。 多个局部掺杂区域间隔地位于下表面上。 第二钝化层位于下表面，并且具有分别对应于局部掺杂区域设置的多个开口。 后电极位于与半导体衬底相对的第二钝化层的一侧上，并且经由开口穿过第二钝化层以接触局部掺杂区域。 对应于前电极的至少一个开口的宽度大于其余开口的宽度。

公开(公告)号：US20070045610A1

公开(公告)日：2007-03-01

申请号：US11293275

申请日：2005-12-05

Applicant: Min-Hung Lee ,  Cheng-Yeh Yu ,  Chee-Wee Liu

Inventor： Min-Hung Lee ,  Cheng-Yeh Yu ,  Chee-Wee Liu

IPC: H01L31/109

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66583 ,  H01L29/78

Abstract: A transistor device with strained Ge layer by selectively growth and a fabricating method thereof are provided. A strained Ge layer is selectively grown on a substrate, so that the material of source/drain region is still the same as that of the substrate, and the strained Ge layer serves as a carry transport channel. Therefore, the performance of the device characteristics can be improved and the leakage current of the transistor may be approximately commensurate with that of a Si substrate field effect transistor (FET).

Abstract translation: 提供了通过选择性生长具有应变Ge层的晶体管器件及其制造方法。 应变Ge层选择性地生长在衬底上，使得源极/漏极区的材料与衬底的材料仍然相同，并且应变Ge层用作携带传输沟道。 因此，可以提高器件特性的性能，并且晶体管的漏电流可以与Si衬底场效应晶体管（FET）的漏电流近似相当。

公开(公告)号：US20120097246A1

公开(公告)日：2012-04-26

申请号：US13074015

申请日：2011-03-29

Applicant: Chee-Wee Liu ,  Wei-Shuo Ho ,  Yen-Yu Chen ,  Chun-Yuan Ku ,  Zhen-Cheng Wu ,  Shuo-Wei Liang ,  Jen-Chieh Chen ,  Chung-Wei Lai ,  Tsung-Pao Chen

Inventor： Chee-Wee Liu ,  Wei-Shuo Ho ,  Yen-Yu Chen ,  Chun-Yuan Ku ,  Zhen-Cheng Wu ,  Shuo-Wei Liang ,  Jen-Chieh Chen ,  Chung-Wei Lai ,  Tsung-Pao Chen

IPC: H01L31/036 ,  H01L31/20

CPC classification number: H01L31/1804 ,  H01L31/068 ,  Y02E10/547 ,  Y02P70/521

Abstract: A solar cell includes a crystalline semiconductor substrate; a first crystalline semiconductor layer; an amorphous semiconductor layer; a first metal electrode layer and a second metal electrode layer. The crystalline semiconductor substrate has a first surface and a second surface, and the crystalline semiconductor substrate has a first doped type. The first crystalline semiconductor layer is disposed on the first surface of the crystalline semiconductor substrate, where the first crystalline semiconductor layer has a second doped type contrary to the first doped type. The amorphous semiconductor layer is disposed on the first crystalline semiconductor layer, and the amorphous semiconductor layer has the second doped type. The first metal electrode layer is disposed on the amorphous semiconductor layer. The second metal electrode layer is disposed on the second surface of the crystalline semiconductor substrate.

Abstract translation: 太阳能电池包括晶体半导体衬底; 第一晶体半导体层; 非晶半导体层; 第一金属电极层和第二金属电极层。 晶体半导体衬底具有第一表面和第二表面，并且晶体半导体衬底具有第一掺杂型。 第一晶体半导体层设置在晶体半导体衬底的第一表面上，其中第一晶体半导体层具有与第一掺杂类型相反的第二掺杂型。 非晶半导体层设置在第一结晶半导体层上，非晶半导体层具有第二掺杂型。 第一金属电极层设置在非晶半导体层上。 第二金属电极层设置在晶体半导体衬底的第二表面上。

公开(公告)号：US07371628B2

公开(公告)日：2008-05-13

申请号：US11228340

申请日：2005-09-19

Applicant: Cha-Hsin Lin ,  Zing-Way Pei ,  Chee-Wee Liu

Inventor： Cha-Hsin Lin ,  Zing-Way Pei ,  Chee-Wee Liu

IPC: H01L21/336

CPC classification number: H01L21/823828 ,  H01L21/823807

Abstract: A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second patterned high stress layer on the semiconductor device. According to the method, the characteristics of the PMOS and the NMOS transistors formed on the same wafer may be improved simultaneously, by utilizing the stress of the patterned layers of high stress material. Further, the mobility of the carriers is enhanced, so that the output characteristic of the transistors can be improved.

Abstract translation: 提供一种制造半导体器件的方法。 该方法主要包括以下步骤：在硅衬底下方形成至少一个第一图案化的高应力层，然后在衬底上形成半导体器件，并在半导体器件上形成至少一个第二图案化的高应力层。 根据该方法，通过利用高应力材料的图案化层的应力，可以同时改善形成在同一晶片上的PMOS和NMOS晶体管的特性。 此外，载流子的迁移率增强，从而可以提高晶体管的输出特性。

公开(公告)号：US20080023733A1

公开(公告)日：2008-01-31

申请号：US11860362

申请日：2007-09-24

Applicant: Min-Hung LEE ,  Cheng-Yeh Yu ,  Shing-Chii Lu ,  Chee-Wee Liu

Inventor： Min-Hung LEE ,  Cheng-Yeh Yu ,  Shing-Chii Lu ,  Chee-Wee Liu

IPC: H01L29/78

CPC classification number: H01L21/26506 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/938

Abstract: Fabrication methods for compressive strained-silicon by ion implantation. Ions are implanted into a silicon-containing substrate and high temperature processing converts the vicinity of the ion-contained region into strained-silicon. Transistors fabricated by the method are also provided.

Abstract translation: 通过离子注入制备压应变硅的制备方法。 将离子注入到含硅衬底中，并且高温处理将离子包含区域的附近转变为应变硅。 还提供了通过该方法制造的晶体管。

公开(公告)号：US20060284164A1

公开(公告)日：2006-12-21

申请号：US11216179

申请日：2005-09-01

Applicant: Min-Hung Lee ,  Cheng-Yeh Yu ,  Chee-Wee Liu

Inventor： Min-Hung Lee ,  Cheng-Yeh Yu ,  Chee-Wee Liu

IPC: H01L31/00

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262

Abstract: A strained germanium field effect transistor (FET) and method of making the same, comprise forming a germanium layer on a substrate, then forming a Si protective layer on the germanium layer, next forming a gate insulation layer on the Si protective layer, and fmally positioning a gate on the gate insulation layer. The germanium layer is used as a carrier transport channel of the strained germanium FET to improve the drive current and the carrier mobility, and to increase the devices performance effectively. And because the Si protective layer is on the germanium layer, the interface property between the germanium layer and the gate insulation layer is improved.

Abstract translation: 应变锗场效应晶体管（FET）及其制造方法包括在衬底上形成锗层，然后在锗层上形成Si保护层，接着在Si保护层上形成栅极绝缘层，并且最终形成 在栅极绝缘层上定位栅极。 锗层用作应变锗FET的载流子传输通道，以提高驱动电流和载流子迁移率，并有效提高器件性能。 并且由于Si保护层在锗层上，所以锗层和栅极绝缘层之间的界面性能得到改善。

公开(公告)号：US20060263959A1

公开(公告)日：2006-11-23

申请号：US11228340

申请日：2005-09-19

Applicant: Cha-Hsin Lin ,  Zing-Way Pei ,  Chee-Wee Liu

Inventor： Cha-Hsin Lin ,  Zing-Way Pei ,  Chee-Wee Liu

IPC: H01L21/8234

CPC classification number: H01L21/823828 ,  H01L21/823807

Abstract: A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second patterned high stress layer on the semiconductor device. According to the method, the characteristics of the PMOS and the NMOS transistors formed on the same wafer may be improved simultaneously, by utilizing the stress of the patterned layers of high stress material. Further, the mobility of the carriers is enhanced, so that the output characteristic of the transistors can be improved.

Abstract translation: 提供一种制造半导体器件的方法。 该方法主要包括以下步骤：在硅衬底下方形成至少一个第一图案化的高应力层，然后在衬底上形成半导体器件，并在半导体器件上形成至少一个第二图案化的高应力层。 根据该方法，通过利用高应力材料的图案化层的应力，可以同时改善形成在同一晶片上的PMOS和NMOS晶体管的特性。 此外，载流子的迁移率增强，从而可以提高晶体管的输出特性。