利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

32 条记录 (耗时 0.022 秒)

    Integrated circuit transistor insulating region fabrication method
    5.
    发明授权
    Integrated circuit transistor insulating region fabrication method 有权
    集成电路晶体管绝缘区制造方法

    公开(公告)号：US07384836B2

    公开(公告)日：2008-06-10

    申请号：US11505957

    申请日：2006-08-17

    申请人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

    发明人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/0852 ,  H01L21/74 ,  H01L21/7621 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

    摘要翻译： 提供集成电路的晶体管。 在第一有源区的阱层中形成第一掺杂阱区。 第一掺杂阱区的至少一部分与晶体管的栅电极相邻。 在第一掺杂阱区中形成凹槽，并且凹槽优选地具有至少约500埃的深度。 第一隔离部分至少部分地在隔离区域上形成在阱层的上表面上。 至少部分地在第一掺杂阱区的凹部中形成第二隔离部分。 第二隔离部分的至少一部分比第一隔离部分低。 漏极掺杂区形成在第一掺杂阱区的凹槽中。 第二隔离部分位于栅电极和漏极掺杂区之间。

    Isolation-region configuration for integrated-circuit transistor
    6.
    发明授权
    Isolation-region configuration for integrated-circuit transistor 有权
    集成电路晶体管的隔离区配置

    公开(公告)号：US07122876B2

    公开(公告)日：2006-10-17

    申请号：US10916133

    申请日：2004-08-11

    申请人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

    发明人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

    IPC分类号： H01L29/00

    CPC分类号： H01L29/0852 ,  H01L21/74 ,  H01L21/7621 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

    摘要翻译： 提供集成电路的晶体管。 在第一有源区的阱层中形成第一掺杂阱区。 第一掺杂阱区的至少一部分与晶体管的栅电极相邻。 在第一掺杂阱区中形成凹槽，并且凹槽优选地具有至少约500埃的深度。 第一隔离部分至少部分地在隔离区域上形成在阱层的上表面上。 至少部分地在第一掺杂阱区的凹部中形成第二隔离部分。 第二隔离部分的至少一部分比第一隔离部分低。 漏极掺杂区形成在第一掺杂阱区的凹槽中。 第二隔离部分位于栅电极和漏极掺杂区之间。

    Isolation structure in field device
    7.
    发明申请
    Isolation structure in field device 有权
    现场设备中的隔离结构

    公开(公告)号：US20060157816A1

    公开(公告)日：2006-07-20

    申请号：US11331442

    申请日：2006-01-12

    申请人： You-Kuo Wu ,  An-Min Chiang ,  Shun-Liang Hsu

    发明人： You-Kuo Wu ,  An-Min Chiang ,  Shun-Liang Hsu

    IPC分类号： H01L21/76 ,  H01L29/00

    CPC分类号： H01L21/76218

    摘要： A semiconductor device. The semiconductor device comprises an isolation structure and two heavily doped regions of a second conductivity type spaced apart from each other by the isolation structure. The isolation structure comprises an isolation region in a semiconductor substrate and a heavily doped region of the first conductivity type. The isolation region has an opening and the heavily doped region of the first conductivity type is substantially surrounded by the opening of the isolation region.

    摘要翻译： 半导体器件。 半导体器件包括隔离结构和通过隔离结构彼此隔开的第二导电类型的两个重掺杂区域。 隔离结构包括半导体衬底中的隔离区和第一导电类型的重掺杂区。 隔离区域具有开口，并且第一导电类型的重掺杂区域基本上被隔离区域的开口包围。

    Method of making and structure for LDMOS transistor
    8.
    发明申请
    Method of making and structure for LDMOS transistor 有权
    LDMOS晶体管的制造和结构方法

    公开(公告)号：US20060033155A1

    公开(公告)日：2006-02-16

    申请号：US10916133

    申请日：2004-08-11

    申请人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

    发明人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/0852 ,  H01L21/74 ,  H01L21/7621 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

    摘要翻译： 提供集成电路的晶体管。 在第一有源区的阱层中形成第一掺杂阱区。 第一掺杂阱区的至少一部分与晶体管的栅电极相邻。 在第一掺杂阱区中形成凹槽，并且凹槽优选地具有至少约500埃的深度。 第一隔离部分至少部分地在隔离区域上形成在阱层的上表面上。 至少部分地在第一掺杂阱区的凹部中形成第二隔离部分。 第二隔离部分的至少一部分比第一隔离部分低。 漏极掺杂区形成在第一掺杂阱区的凹槽中。 第二隔离部分位于栅电极和漏极掺杂区之间。

    Isolation structure in field device
    9.
    发明授权
    Isolation structure in field device 有权
    现场设备中的隔离结构

    公开(公告)号：US07911022B2

    公开(公告)日：2011-03-22

    申请号：US11331442

    申请日：2006-01-12

    申请人： You-Kuo Wu ,  An-Min Chiang ,  Shun-Liang Hsu

    发明人： You-Kuo Wu ,  An-Min Chiang ,  Shun-Liang Hsu

    IPC分类号： H01L21/70

    CPC分类号： H01L21/76218

    摘要： A semiconductor device. The semiconductor device comprises an isolation structure and two heavily doped regions of a second conductivity type spaced apart from each other by the isolation structure. The isolation structure comprises an isolation region in a semiconductor substrate and a heavily doped region of the first conductivity type. The isolation region has an opening and the heavily doped region of the first conductivity type is substantially surrounded by the opening of the isolation region.

    摘要翻译： 半导体器件。 半导体器件包括隔离结构和通过隔离结构彼此隔开的第二导电类型的两个重掺杂区域。 隔离结构包括半导体衬底中的隔离区和第一导电类型的重掺杂区。 隔离区域具有开口，并且第一导电类型的重掺杂区域基本上被隔离区域的开口包围。

    Integrated circuit transistor insulating region fabrication method
    10.
    发明申请
    Integrated circuit transistor insulating region fabrication method 有权
    集成电路晶体管绝缘区制造方法

    公开(公告)号：US20060286735A1

    公开(公告)日：2006-12-21

    申请号：US11505957

    申请日：2006-08-17

    申请人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

    发明人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/0852 ,  H01L21/74 ,  H01L21/7621 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

    摘要翻译： 提供集成电路的晶体管。 在第一有源区的阱层中形成第一掺杂阱区。 第一掺杂阱区的至少一部分与晶体管的栅电极相邻。 在第一掺杂阱区中形成凹槽，并且凹槽优选地具有至少约500埃的深度。 第一隔离部分至少部分地在隔离区域上形成在阱层的上表面上。 至少部分地在第一掺杂阱区的凹部中形成第二隔离部分。 第二隔离部分的至少一部分比第一隔离部分低。 漏极掺杂区形成在第一掺杂阱区的凹槽中。 第二隔离部分位于栅电极和漏极掺杂区之间。