公开(公告)号：US20110001768A1

公开(公告)日：2011-01-06

申请号：US12822914

申请日：2010-06-24

申请人： Chen-Nan Lin ,  Ming-Chieh Yeh ,  Chun Wen Yeh ,  Chun-Chia Chen

发明人： Chen-Nan Lin ,  Ming-Chieh Yeh ,  Chun Wen Yeh ,  Chun-Chia Chen

IPC分类号： G09G5/02

CPC分类号： G09G3/3685 ,  G09G2310/0221 ,  G09G2310/027 ,  G09G2352/00

摘要： A display controller, video signal transmitting method and system thereof are provided. The display controller includes a processing circuit; a transmitting channel, coupled to the processing circuit; a receiving channel, coupled to the processing circuit; and a clock generator, that generates an internal clock signal and an external clock signal. Upon receiving a video signal, the processing circuit processes a first partial pixel data of the video signal to output a first display control signal. The transmitting channel converts a second partial pixel data of the video signal to a partial video signal having a multiple data rate according to the internal clock signal to be outputted.

摘要翻译： 提供了显示控制器，视频信号发送方法及其系统。 显示控制器包括处理电路; 耦合到所述处理电路的发送信道; 耦合到所述处理电路的接收信道; 以及产生内部时钟信号和外部时钟信号的时钟发生器。 在接收到视频信号时，处理电路处理视频信号的第一部分像素数据以输出第一显示控制信号。 发送信道根据要输出的内部时钟信号将视频信号的第二部分像素数据转换为具有多数据速率的部分视频信号。

公开(公告)号：US09805685B2

公开(公告)日：2017-10-31

申请号：US12822914

申请日：2010-06-24

申请人： Chen-Nan Lin ,  Ming-Chieh Yeh ,  Chun Wen Yeh ,  Chun-Chia Chen

发明人： Chen-Nan Lin ,  Ming-Chieh Yeh ,  Chun Wen Yeh ,  Chun-Chia Chen

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G2310/0221 ,  G09G2310/027 ,  G09G2352/00

摘要： A display controller, video signal transmitting method and system thereof are provided. The display controller includes a processing circuit; a transmitting channel, coupled to the processing circuit; a receiving channel, coupled to the processing circuit; and a clock generator, that generates an internal clock signal and an external clock signal. Upon receiving a video signal, the processing circuit processes a first partial pixel data of the video signal to output a first display control signal. The transmitting channel converts a second partial pixel data of the video signal to a partial video signal having a multiple data rate according to the internal clock signal to be outputted.

公开(公告)号：US20110131354A1

公开(公告)日：2011-06-02

申请号：US12947966

申请日：2010-11-17

申请人： Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

发明人： Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

IPC分类号： G06F13/38

CPC分类号： G06F17/5068

摘要： A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

摘要翻译： 通用存储器I / O生成装置包括定义模块，检索模块，生成模块和布局模块。 定义模块根据多个I / O的引脚配置来定义映射表。 映射表包括多个IO和多个存储器功能之间的对应关系。 检索模块从与多个I / O和多个存储器功能之间的对应关系相关联的候选信息中检索对应于映射表的控制信息。 生成模块根据控制信息生成硬件描述语言（HDL）文件。 布局模块根据HDL文件对多个I / O进行编程，使得每个I / O可以对应于其相应的存储器功能。

公开(公告)号：US08635569B2

公开(公告)日：2014-01-21

申请号：US12947966

申请日：2010-11-17

申请人： Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

发明人： Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

摘要翻译： 通用存储器I / O生成装置包括定义模块，检索模块，生成模块和布局模块。 定义模块根据多个I / O的引脚配置来定义映射表。 映射表包括多个IO和多个存储器功能之间的对应关系。 检索模块从与多个I / O和多个存储器功能之间的对应关系相关联的候选信息中检索与映射表相对应的控制信息。 生成模块根据控制信息生成硬件描述语言（HDL）文件。 布局模块根据HDL文件对多个I / O进行编程，使得每个I / O可以对应于其相应的存储器功能。

公开(公告)号：US09338458B2

公开(公告)日：2016-05-10

申请号：US13216273

申请日：2011-08-24

申请人： Min-Hao Chiu ,  Chia-Yun Cheng ,  Chun-Chia Chen

发明人： Min-Hao Chiu ,  Chia-Yun Cheng ,  Chun-Chia Chen

IPC分类号： H04N7/26 ,  H04N19/124 ,  H04N19/129 ,  H04N19/12

CPC分类号： H04N19/176 ,  H04N19/12 ,  H04N19/122 ,  H04N19/124 ,  H04N19/129 ,  H04N19/13

摘要： An exemplary video decoding apparatus includes a first decoding unit configured for decoding a first encoded block to generate first residual values, a first detecting unit configured for detecting whether all of the first residual values have a same first value, a first processing circuit configured for processing the first residual values to generate first processed residual values, and a second processing circuit configured for generating a decoded block corresponding to the first encoded block. When all of the first residual values have the same first value, the first detecting unit controls the second processing circuit to generate the decoded block without referring to the first processed residual values.

摘要翻译： 示例性视频解码装置包括：第一解码单元，被配置为对第一编码块进行解码以产生第一残差值;第一检测单元，被配置为检测所有第一残差值是否都具有相同的第一值;第一处理电路， 产生第一处理残差的第一残差值，以及被配置为产生与第一编码块对应的解码块的第二处理电路。 当所有第一残差值都具有相同的第一值时，第一检测单元控制第二处理电路以生成解码块而不参照第一处理残差值。

公开(公告)号：US20130234216A1

公开(公告)日：2013-09-12

申请号：US13414375

申请日：2012-03-07

申请人： Ying-Hung Chou ,  Shao-Hua Hsu ,  Chi-Horn Pai ,  Zen-Jay Tsai ,  Shih-Hao Su ,  Chun-Chia Chen ,  Shih-Chieh Hsu ,  Chih-Chung Chen

发明人： Ying-Hung Chou ,  Shao-Hua Hsu ,  Chi-Horn Pai ,  Zen-Jay Tsai ,  Shih-Hao Su ,  Chun-Chia Chen ,  Shih-Chieh Hsu ,  Chih-Chung Chen

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.

摘要翻译： 对半导体装置的制造方法进行说明。 在衬底上形成栅极层，C掺杂的第一保护层和硬掩模层，然后图案化以在第一区域中形成第一堆叠，在第二区域中形成第二堆叠。 在第一和第二堆叠的侧壁上形成第二保护层。 阻挡层形成在第一区域中，第一隔离物形成在第二区域中的第二堆叠的侧壁上的第二保护层的侧壁上。 在第一间隔物旁边的基板中形成半导体化合物。 去除阻挡层和第一间隔物。 第一堆叠中的硬掩模层和第二堆叠被去除。

公开(公告)号：US20100046629A1

公开(公告)日：2010-02-25

申请号：US12193760

申请日：2008-08-19

申请人： Chun-Chia Chen ,  Chi-Cheng Ju

发明人： Chun-Chia Chen ,  Chi-Cheng Ju

IPC分类号： H04N11/02 ,  G06K9/46

CPC分类号： H04N19/59 ,  H04N19/427 ,  H04N19/44 ,  H04N19/51

摘要： A video decoding method includes: (a) computing location relations between an original frame and a resized frame to which the frame is to be scaled; (b) mapping a location of a data unit of the original frame to a location of a corresponding data unit of the resized frame according to the location relations; and (c) scaling the data unit of the original frame to the corresponding data unit of the resized frame.

摘要翻译： 视频解码方法包括：（a）计算原始帧与要缩放帧的调整大小的帧之间的位置关系; （b）根据位置关系将原始帧的数据单元的位置映射到调整大小的帧的相应数据单元的位置; 和（c）将原始帧的数据单元缩放到调整大小的帧的相应数据单元。

公开(公告)号：US20070042584A1

公开(公告)日：2007-02-22

申请号：US11161756

申请日：2005-08-16

申请人： Jen-Hong Huang ,  Nien-Chung Li ,  Yi-Chung Sheng ,  Chun-Chia Chen

发明人： Jen-Hong Huang ,  Nien-Chung Li ,  Yi-Chung Sheng ,  Chun-Chia Chen

IPC分类号： H01L21/44

CPC分类号： H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： At least one gate electrode is formed on a substrate. A first dielectric layer and a second dielectric layer are formed on the gate electrode, respectively. A portion of the second dielectric layer is removed to form a spacer on either side of the gate electrode. A portion of the first dielectric layer is removed to form a notch between the gate electrode and the spacer, the notch having an aspect ratio greater than 1. A self-aligned silicide process is performed to form a silicide on exposed surfaces of the gate electrode and the first dielectric layer underneath the notch.

公开(公告)号：US08456209B2

公开(公告)日：2013-06-04

申请号：US12956138

申请日：2010-11-30

申请人： Chun-Chia Chen ,  Sterling Smith

发明人： Chun-Chia Chen ,  Sterling Smith

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： A delay locked loop includes a pulse generator, a delay unit, a phase detector and a control unit. The pulse generator generates a pulse signal and a determination signal according to an input clock signal. The delay unit delays the pulse signal according to a digital control signal to generate a delayed pulse signal. The phase detector detects a time delay of the delayed pulse signal according to the determination signal to generate a detection result. The control unit generates a digital control signal according to the detection result to control the delayed pulse signal by a delay amount.

摘要翻译： 延迟锁定环包括脉冲发生器，延迟单元，相位检测器和控制单元。 脉冲发生器根据输入时钟信号产生脉冲信号和确定信号。 延迟单元根据数字控制信号延迟脉冲信号以产生延迟的脉冲信号。 相位检测器根据确定信号检测延迟的脉冲信号的时间延迟，以产生检测结果。 控制单元根据检测结果生成数字控制信号，以将延迟的脉冲信号控制一个延迟量。

公开(公告)号：US08345763B2

公开(公告)日：2013-01-01

申请号：US12104583

申请日：2008-04-17

申请人： Chun-Chia Chen ,  Chi-Cheng Ju ,  Chih-Ming Wang

发明人： Chun-Chia Chen ,  Chi-Cheng Ju ,  Chih-Ming Wang

IPC分类号： H04N7/12

CPC分类号： H04N19/55 ,  H04N19/51 ,  H04N19/61

摘要： An integrated circuit capable of motion compensation and a method thereof. The integrated circuit includes a partition unit and a motion compensation unit. The partition unit receives a video block having a predetermined block dimension, and partitions the video block into sub-blocks with a sub-block dimension less than the predetermined block dimension when the video block is on a frame boundary of a video frame. The motion compensation unit, coupled to the partition unit, performs motion compensation on the sub-blocks.

摘要翻译： 一种能够进行运动补偿的集成电路及其方法。 集成电路包括分区单元和运动补偿单元。 分割单元接收具有预定块尺寸的视频块，并且当视频块在视频帧的帧边界上时，将视频块分割成子块尺寸小于预定块尺寸的子块。 耦合到分割单元的运动补偿单元对子块执行运动补偿。