公开(公告)号：US5130266A

公开(公告)日：1992-07-14

申请号：US573814

申请日：1990-08-28

申请人： Cheng H. Huang ,  Water Lur

发明人： Cheng H. Huang ,  Water Lur

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/28061 ,  Y10S148/147

摘要： A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the peeling problems of refractory metal silicide layers on a polycide gate. The process of this invention has been simplified by not using several of the high thermal cycle process steps believed to be necessary for successfully making a polycide gate lightly doped drain MOS FET integrated circuit. These steps are (1) the thermal oxidation after the polycide etching step, (2) the densification step after the blanket deposition of silicon dioxide layer for the spacer preparation, and (3) the silicon oxide capping of the refractory metal silicide layer after the spacer formation by anisotropically etching. The result is a process that provides a non-peeling polycide gate lightly doped drain MOS FET integrated circuit device.

摘要翻译： 描述了一种用于制造轻掺杂漏极MOSFET集成电路器件的方法，其克服了多晶硅栅极上难熔金属硅化物层的剥离问题。 通过不使用被认为是成功制造多晶硅栅极轻掺杂漏极MOS FET集成电路所必需的几个高热循环工艺步骤，已经简化了本发明的工艺。 这些步骤是（1）在多晶硅蚀刻步骤之后的热氧化，（2）在用于间隔物制备的二氧化硅层的覆盖沉积之后的致密化步骤，和（3）耐火金属硅化物层之后的氧化硅封盖 通过各向异性蚀刻形成间隔物。 结果是提供非剥离多晶硅栅极轻掺杂漏极MOS FET集成电路器件的工艺。

公开(公告)号：US5393704A

公开(公告)日：1995-02-28

申请号：US165337

申请日：1993-12-13

申请人： Cheng H. Huang ,  Water Lur

发明人： Cheng H. Huang ,  Water Lur

IPC分类号： H01L21/28 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/28 ,  Y10S148/02

摘要： A method of forming a self-aligned trenched contact in the fabrication of an integrated circuit is described. Semiconductor device regions are formed in and on a semiconductor substrate wherein the semiconductor device regions include gate electrodes on the surface of the semiconductor substrate and source/drain regions within the semiconductor substrate. Spacers are formed on the sidewalls of the gate electrodes. A layer of silicon oxide is deposited over the surface of the substrate wherein the silicon oxide contacts the source/drain regions within the substrate between the gate electrodes. The substrate is covered with a layer of photoresist which is patterned to provide an opening over the planned self-aligned trenched contact between the gate electrodes. The silicon oxide is etched away to provide an opening to the silicon substrate using the patterned photoresist and the sidewall spacers as a mask. A trench is etched into the silicon substrate within the opening using the photoresist and the sidewall spacers as a mask to form the self-aligned trenched contact opening. A conducting layer is deposited within the trenched opening to complete the contact in the manufacture of the integrated circuit device.

摘要翻译： 描述了在集成电路的制造中形成自对准沟槽接触的方法。 半导体器件区域形成在半导体衬底中和半导体衬底上，其中半导体器件区域包括在半导体衬底的表面上的栅电极和半导体衬底内的源极/漏极区域。 隔板形成在栅电极的侧壁上。 在衬底的表面上沉积氧化硅层，其中氧化硅与栅电极之间的衬底内的源/漏区接触。 衬底被一层光致抗蚀剂覆盖，其被图案化以在栅极之间的预定的自对准沟槽接触提供开口。 蚀刻掉氧化硅，以使用图案化的光致抗蚀剂和侧壁间隔物作为掩模提供到硅衬底的开口。 使用光致抗蚀剂和侧壁间隔物作为掩模，在开口内的硅衬底中蚀刻沟槽，以形成自对准沟槽接触开口。 导电层沉积在沟槽开口内以在集成电路器件的制造中完成接触。

公开(公告)号：US5374586A

公开(公告)日：1994-12-20

申请号：US127053

申请日：1993-09-27

申请人： Cheng H. Huang ,  Water Lur

发明人： Cheng H. Huang ,  Water Lur

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/32 ,  H01L21/76221

摘要： A new method of local oxidation using a multiple process is described. A thin silicon oxide layer is formed over the surface of a silicon substrate. A layer of silicon nitride is deposited overlying the silicon oxide layer. The silicon oxide and silicon nitride layers are patterned to provide openings of the smallest size exposing portions of the silicon substrate to he oxidized and growing field oxide regions within these smallest size openings. The patterning and growing of field oxide regions is repeated for each larger size of opening required. The silicon nitride and silicon oxide layers are removed, thereby completing local oxidation of the integrated circuit.

摘要翻译： 描述了使用多个过程的局部氧化的新方法。 在硅衬底的表面上形成薄的氧化硅层。 覆盖在氧化硅层上的氮化硅层被沉积。 将氧化硅和氮化硅层图案化以提供最小尺寸的硅衬底暴露部分的开口，使其在这些最小尺寸的开口内被氧化和生长的场氧化物区域。 对于所需的每个更大尺寸的开口，重复场氧化物区域的图案化和生长。 去除氮化硅和氧化硅层，从而完成集成电路的局部氧化。

公开(公告)号：US5371036A

公开(公告)日：1994-12-06

申请号：US241337

申请日：1994-05-11

申请人： Water Lur ,  Cheng H. Huang

发明人： Water Lur ,  Cheng H. Huang

IPC分类号： H01L21/32 ,  H01L21/762 ,  H21L21/76

CPC分类号： H01L21/32 ,  H01L21/7621

摘要： A new method of local oxidation by means of stress-releasing narrow trenches is described. Pad silicon oxide, silicon nitride, and silicon dioxide layers are formed on a silicon substrate. Portions of these layers not covered by a mask are etched away to provide an opening to the silicon substrate where the field oxidation region is to be formed. The silicon substrate is etched into where it is exposed to form a shallow trench within the opening. Silicon dioxide spacers and silicon nitride spacers are formed on the sidewalls of the opening. The silicon substrate is coated with a spin-on-glass layer. The spin-on-glass layer is cured, then etched back so that the spin-on-glass layer remains only within the shallow trench not covered by the spacers. The silicon nitride spacers are stripped away. Narrow trenches are etched into the silicon substrate under the silicon nitride spacers. The silicon dioxide spacers and spin-on-glass layer are removed leaving the opening entirely exposed. Channel-stops are selectively ion implanted through the opening into the substrate underneath the trenches. The silicon substrate is oxidized within the opening wherein the silicon substrate is transformed to silicon dioxide and wherein the silicon dioxide expands to fill the narrow trenches. The narrow trenches act to relieve stress within the silicon substrate. The silicon dioxide expands vertically to provide a fully recessed surface of the field oxidation region.

摘要翻译： 描述了通过应力释放窄沟槽进行局部氧化的新方法。 在硅衬底上形成衬垫氧化硅，氮化硅和二氧化硅层。 这些层未被掩模覆盖的部分被蚀刻掉以提供要形成场氧化区的硅衬底的开口。 将硅衬底蚀刻到其暴露的部分，以在开口内形成浅沟槽。 二氧化硅间隔物和氮化硅间隔物形成在开口的侧壁上。 硅衬底涂有旋涂玻璃层。 旋涂玻璃层固化，然后回蚀，使得旋涂玻璃层仅保留在未被间隔物覆盖的浅沟槽内。 剥离氮化硅间隔物。 在氮化硅间隔物下方的硅衬底中蚀刻窄沟槽。 去除二氧化硅间隔物和旋涂玻璃层，使开口完全暴露。 通道通孔通过开口选择性离子注入到沟槽下方的衬底中。 硅衬底在开口内被氧化，其中硅衬底转变成二氧化硅，并且其中二氧化硅膨胀以填充窄沟槽。 窄沟槽起到减轻硅衬底内的应力的作用。 二氧化硅垂直膨胀以提供场氧化区的完全凹陷的表面。

公开(公告)号：US5554566A

公开(公告)日：1996-09-10

申请号：US301537

申请日：1994-09-06

申请人： Water Lur ,  Cheng H. Huang

发明人： Water Lur ,  Cheng H. Huang

IPC分类号： H01L21/28 ,  H01L21/768

CPC分类号： H01L21/76889 ,  H01L21/28061

摘要： A method for forming MOSFET devices, with an improved polycide gate has been accomplished. The polycide structure, made with metal silicide on polysilicon has a reduced rate of adhesion loss or peeling of the metal silicide from the underlying polysilicon, due to the unique surface of the polysilicon. The desired surface of the polysilicon, that will reduce the peeling phenomena, is a wavy or undulated surface. This is accomplished by either depositing the polysilicon at conditions that result in a hemi-spherical grained surface, or obtaining a similar wavy or undulated surface by treating smooth polysilicon in either phosphoric acid or by anodization in hydrofluoric acid. The adhesion of the subsequent metal silicide to the wavy surface of the polysilicon is improved to a point where peeling of the metal silicide from the underlying polysilicon is eliminated.

摘要翻译： 已经实现了用于形成具有改进的多晶硅栅极的MOSFET器件的方法。 由于多晶硅的独特表面，由多晶硅上的金属硅化物制成的多晶硅结构具有降低的粘附损失率或金属硅化物从下面的多晶硅的剥离。 多晶硅的期望的表面，其将减少剥离现象，是波浪形或波浪形的表面。 这可以通过在导致半球形颗粒表面的条件下沉积多晶硅，或通过在磷酸中处理光滑多晶硅或通过在氢氟酸中阳极氧化获得类似的波浪或波浪表面来实现。 随后的金属硅化物对多晶硅的波浪表面的粘附性得到改善，从而消除了金属硅化物与下面的多晶硅的剥离。

公开(公告)号：US5457065A

公开(公告)日：1995-10-10

申请号：US355490

申请日：1994-12-14

申请人： Cheng H. Huang ,  Water Lur

发明人： Cheng H. Huang ,  Water Lur

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for fabricating a stacked storage capacitor on a dynamic random access memory (DRAM) cell with increased capacitance was accomplished. The stacked capacitor is used with a field effect transistor (FET) as part of a dynamic random access memory (DRAM) cell for storing data in the form of stored charge on the capacitor. The method for making the capacitor involves forming a bottom electrode from a single polysilicon layer having a fin-shaped structure, and then using a second polysilicon layer and a plasma etch back to create a second self-aligned fin-like structure that significantly increases the surface area of the capacitor bottom electrode. The capacitor structure is then completed by forming a thin capacitor dielectric layer on the bottom electrode and depositing a third polysilicon layer to form the top electrode and complete the capacitor with significantly increased capacitance and an economy of processing steps.

摘要翻译： 实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造堆叠存储电容器的方法。 叠层电容器与作为动态随机存取存储器（DRAM）单元的一部分的场效应晶体管（FET）一起使用，用于以电容器上的存储电荷的形式存储数据。 用于制造电容器的方法包括从具有鳍状结构的单个多晶硅层形成底部电极，然后使用第二多晶硅层和等离子体回蚀以产生第二自对准鳍状结构，其显着增加 电容器底部电极的表面积。 然后通过在底部电极上形成薄的电容器电介质层并沉积第三多晶硅层以形成顶部电极并且以显着增加的电容和经济的加工步骤完成电容器来完成电容器结构。

公开(公告)号：US5384268A

公开(公告)日：1995-01-24

申请号：US7713

申请日：1993-01-22

申请人： Water Lur ,  Ben Chen ,  Cheng H. Huang

发明人： Water Lur ,  Ben Chen ,  Cheng H. Huang

IPC分类号： H01L21/265

CPC分类号： H01L21/265 ,  H01L21/2652

摘要： A method is described for fabricating an integrated circuit in which the gate electrodes and gate dielectric silicon oxide are protected from electrical charge damage during ion implantation. A thin conducting layer is deposited over the pattern of gate electrodes/gate dielectric silicon oxide wherein the conducting layer is grounded to the silicon substrate. The high-dose ion implantation is applied through the conducting layer which layer grounds the electrical charge resulting from the ion implantation, and hence protects the gate electrodes from charge damage. The electron "flood gun" need not be used.

摘要翻译： 描述了一种用于制造集成电路的方法，其中栅极电极和栅极电介质氧化硅在离子注入期间被保护免受电荷损伤。 在栅电极/栅极电介质氧化硅的图案上沉积薄导电层，其中导电层接地到硅衬底。 通过导电层施加高剂量离子注入，该层将离子注入产生的电荷接地，从而保护栅极免受电荷损伤。 电子“喷枪”不需要使用。

公开(公告)号：US5449644A

公开(公告)日：1995-09-12

申请号：US181298

申请日：1994-01-13

申请人： Gary Hong ,  Cheng H. Huang ,  Ming-Tzong Yang ,  Hong-Tsz Pan

发明人： Gary Hong ,  Cheng H. Huang ,  Ming-Tzong Yang ,  Hong-Tsz Pan

IPC分类号： H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76802 ,  Y10S148/133

摘要： A new method of forming a contact opening by using a sacrificial spin-on-glass layer is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A glasseous layer is deposited over the uneven surface of the substrate and reflowed at low temperature whereby the glasseous layer will have a trench shaped surface over the planned contact opening area. The glasseous layer is covered with a spin-on-glass layer wherein the spin-on-glass planarizes the surface of the substrate. The spin-on-glass layer is baked and then covered with a uniform thickness layer of photoresist. The photoresist layer is exposed and developed to form the desired photoresist mask for the contact opening. The exposed spin-on-glass and glasseous layers are etched away to provide the contact opening to the semiconductor substrate. The photoresist layer is stripped and the sacrificial spin-on-glass layer is removed to complete the formation of the contact opening in the manufacture of the integrated circuit.

摘要翻译： 描述了通过使用牺牲旋涂玻璃层形成接触开口的新方法。 提供半导体衬底，其中衬底的表面具有不平坦的形貌。 在基体的不平坦表面上沉积有胶层，并在低温下回流，由此在层叠的接触开口区域上形成沟槽形表面。 玻璃层被旋涂玻璃层覆盖，其中旋涂玻璃将基材的表面平坦化。 将旋涂玻璃层烘烤，然后用均匀的厚度的光致抗蚀剂层覆盖。 光致抗蚀剂层被曝光和显影以形成用于接触开口的所需光刻胶掩模。 暴露的旋涂玻璃和玻璃层被蚀刻掉以提供到半导体衬底的接触开口。 剥离光致抗蚀剂层，去除牺牲旋涂玻璃层，以在集成电路的制造中完成接触开口的形成。

公开(公告)号：US06897543B1

公开(公告)日：2005-05-24

申请号：US10646013

申请日：2003-08-22

申请人： Cheng H. Huang ,  Yowjuang Liu ,  Chih-Ching Shih ,  Hugh Sung-Ki O

发明人： Cheng H. Huang ,  Yowjuang Liu ,  Chih-Ching Shih ,  Hugh Sung-Ki O

IPC分类号： G11C17/16 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/112 ,  H01L27/12 ,  H01L29/00

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/983 ,  H01L2924/00

摘要： Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

摘要翻译： 提供集成电路反熔丝电路。 金属氧化物半导体（MOS）反熔丝晶体管用作电可编程反熔丝。 在其未编程状态下，反熔丝晶体管截止并具有较高的电阻。 在编程期间，反熔丝晶体管导通，其熔化下面的硅并导致晶体管电阻的永久性降低。 感测电路监视反熔丝晶体管的电阻并相应地提供高或低输出信号。 反熔丝晶体管可以在编程期间通过在其衬底处相对于其源极升高电压而导通。 衬底可以通过电阻器接地。 可能通过使电流流过电阻器而使衬底偏置。 可以通过引起漏极 - 衬底结的雪崩击穿或通过产生连接到电阻器的外部齐纳二极管电路的齐纳击穿来使电流流过电阻器。

公开(公告)号：US06785109B1

公开(公告)日：2004-08-31

申请号：US09756501

申请日：2001-01-08

申请人： Cheng H. Huang ,  Chiakang Sung ,  John Costello

发明人： Cheng H. Huang ,  Chiakang Sung ,  John Costello

IPC分类号： H02H322

CPC分类号： H01L27/0251

摘要： A technique for providing ESD protection for integrated circuit devices with multiple power and/or ground buses is provided. The technique involves using a clamping device that is capable of handling both positive and negative ESD pulses to clamp each power bus, ground bus, and I/O pad within a device to a respective one of the ground buses. Without resorting to exhaustive cross-clamping, this arrangement provides a discharge path for an ESD pulse applied across any combination of power buses, ground buses, and I/O pads during an ESD event.

摘要翻译： 提供了一种用于为具有多个电源和/或接地总线的集成电路器件提供ESD保护的技术。 该技术涉及使用能够处理正和负ESD脉冲的钳位装置，以将设备内的每个电源总线，接地总线和I / O焊盘夹到相应的一个接地总线。 在不采取彻底的交叉钳位的情况下，这种布置为ESD事件期间在电源总线，接地总线和I / O焊盘的任何组合上施加的ESD脉冲提供放电路径。