公开(公告)号：US20050127405A1

公开(公告)日：2005-06-16

申请号：US10733095

申请日：2003-12-11

Applicant: Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang ,  Ya-Yun Liu

Inventor： Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang ,  Ya-Yun Liu

IPC: G06F9/45 ,  H01L23/48 ,  H01L23/52 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L27/11898 ,  H01L27/0207

Abstract: An I/O circuit placement method. In the I/O circuit placement method, at least two rows of I/O circuits are placed on a first side of the chip, and each I/O circuit has a head section and a tail section. The placement direction of the head section and the tail section is perpendicular to the placement direction of the I/O circuits in the rows. The semiconductor further has a core circuit disposed on the chip, wherein the rows of I/O circuits are disposed outside the core circuit and are at the periphery of the chip. Due to the I/O circuit placement in the semiconductor device, the present invention reduces the area of the semiconductor chip and fabrication cost.

Abstract translation: 一种I / O电路放置方法。 在I / O电路放置方法中，至少两行I / O电路放置在芯片的第一侧上，并且每个I / O电路具有头部和尾部。 头部和尾部的放置方向垂直于行中的I / O电路的放置方向。 半导体还具有设置在芯片上的核心电路，其中I / O电路行设置在核心电路的外部并且位于芯片的外围。 由于半导体器件中的I / O电路布置，本发明减小了半导体芯片的面积和制造成本。

公开(公告)号：US06895540B2

公开(公告)日：2005-05-17

申请号：US10064475

申请日：2002-07-18

Applicant: Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang

Inventor： Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang

IPC: G01R31/3185 ,  G01R31/28 ,  G06F9/45 ,  H01L25/00

CPC classification number: G01R31/318594 ,  G01R31/318541

Abstract: A mux scan cell includes a multiplexer having a first input node for receiving raw data, a second input node for receiving test data, an output node, a selection node, and a delay circuit electrically connected between the second input node and the output node for prolonging a traveling time which the test data takes to travel from the second input node to the output node. The mux scan cell also includes a flip-flop connected to the multiplexer. With the delay circuit, the traveling time of the test data is prolonged such that the traveling time which the test data takes to travel from the second input node to the output node simulates a sum of a traveling time in which the raw data travels through a combinational logic and a traveling time in which the raw data travels from the first input node to the output node.

Abstract translation: 多路复用扫描单元包括多路复用器，其具有用于接收原始数据的第一输入节点，用于接收测试数据的第二输入节点，输出节点，选择节点和电连接在第二输入节点和输出节点之间的延迟电路，用于 延长测试数据从第二输入节点到输出节点行进的行进时间。 复用器扫描单元还包括连接到多路复用器的触发器。 利用延迟电路，延长测试数据的行进时间，使得测试数据从第二输入节点行进到输出节点的行进时间模拟原始数据行进通过的行进时间的总和 组合逻辑和原始数据从第一输入节点传播到输出节点的行进时间。

公开(公告)号：US20110316122A1

公开(公告)日：2011-12-29

申请号：US13225756

申请日：2011-09-06

Applicant: Yu-Pin TSAI ,  Cheng-I Huang ,  Yao-Hui Hu

Inventor： Yu-Pin TSAI ,  Cheng-I Huang ,  Yao-Hui Hu

IPC: H01L21/268 ,  H01L29/06

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2223/54433 ,  H01L2224/16 ,  H01L2924/01025 ,  H01L2924/01084 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/00

Abstract: A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon.

Abstract translation: 提供了晶片激光打标方法。 首先，提供具有彼此相对的第一表面（活性表面）和第二表面（背面）的晶片。 接下来，晶片变薄。 然后，将薄的晶片固定在非UV带上，使得晶片的第二表面附接到带上。 最后，执行激光标记步骤，使得激光穿透非UV带并且在晶片的第二表面上标记图案。 根据本实施例的激光标记方法，图案由残留在晶片的第二表面上的非UV残余物形成，并且胶合残余物的成分至少包括硅和碳的元素。

公开(公告)号：US08769451B2

公开(公告)日：2014-07-01

申请号：US13547251

申请日：2012-07-12

Applicant: Ping-Hung Yuh ,  Cheng-I Huang ,  Chung-Hsing Wang

Inventor： Ping-Hung Yuh ,  Cheng-I Huang ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5081

Abstract: In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout.

Abstract translation: 在由至少一个处理器执行的半导体器件设计方法中，提取在半导体器件的布局的区域内的电气元件之间的至少一个第一寄生参数和在布局区域之外的电气元件之间的至少一个第二寄生参数 通过不同的工具。 提取的寄生参数被并入到布局中。

公开(公告)号：US08448120B2

公开(公告)日：2013-05-21

申请号：US13045839

申请日：2011-05-09

Applicant: Cheng-I Huang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

Inventor： Cheng-I Huang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F1/38 ,  G06F17/5081 ,  G06F2217/84 ,  H01L27/0207

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

Abstract translation: 一种方法包括使用电子设计自动化工具执行位置和路线操作，以产生用于形成半导体器件的电路图案的光掩模的初步布局。 位置和路线操作受到多个单一图案化间隔物技术（SPST）路由规则约束。 使用RC提取工具在EDA工具内模拟虚拟导电填充图案，以预测要添加到光掩模的初步布局的虚拟导电填充图案的位置和大小。 基于初步布局和仿真虚拟导电填充图案，在EDA工具中执行电路图案的RC定时分析。

公开(公告)号：US20120288786A1

公开(公告)日：2012-11-15

申请号：US13045839

申请日：2011-05-09

Applicant: Cheng-I Huang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

Inventor： Cheng-I Huang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G03F1/00 ,  G06F17/50 ,  G03F7/20

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F1/38 ,  G06F17/5081 ,  G06F2217/84 ,  H01L27/0207

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

Abstract translation: 一种方法包括使用电子设计自动化工具执行位置和路线操作，以产生用于形成半导体器件的电路图案的光掩模的初步布局。 位置和路线操作受到多个单一图案化间隔物技术（SPST）路由规则约束。 使用RC提取工具在EDA工具内模拟虚拟导电填充图案，以预测要添加到光掩模的初步布局的虚拟导电填充图案的位置和大小。 基于初步布局和仿真虚拟导电填充图案，在EDA工具中执行电路图案的RC定时分析。

公开(公告)号：US20080200037A1

公开(公告)日：2008-08-21

申请号：US11953846

申请日：2007-12-10

Applicant: Yu-Pin Tsai ,  Cheng-I Huang

Inventor： Yu-Pin Tsai ,  Cheng-I Huang

IPC: H01L21/00

CPC classification number: H01L21/304

Abstract: A method of thinning wafer is disclosed. A wafer has an active surface and a back surface is provided. A plurality of protruding components may be disposed on the active surface. The wafer is placed in a mold and a polymeric material is formed in the mold to cover at least the active surface of the wafer. The polymeric material is cured and the mold is removed. The back surface of the wafer is ground to thin the wafer. The polymeric material is removed to expose the active surface of the wafer and the protruding components disposed on the active surface. The polymeric material is allowed to cover the active surface of the wafer and the protruding components through the mold; accordingly, the stress produced during the grinding can be distributed uniformly on the wafer, and the wafer warpage, breakage, or collapse, or the protruding component peeling can be avoided.

Abstract translation: 公开了一种薄化晶片的方法。 晶片具有活性表面并提供后表面。 多个突出部件可以设置在活动表面上。 将晶片放置在模具中，并且在模具中形成聚合物材料以至少覆盖晶片的活性表面。 聚合物材料固化并除去模具。 研磨晶片的背面以使晶片变薄。 去除聚合物材料以暴露晶片的活性表面和设置在活性表面上的突出组分。 允许聚合物材料通过模具覆盖晶片的活性表面和突出的部件; 因此，可以在研磨时产生的应力均匀地分布在晶片上，并且可以避免晶片的翘曲，断裂或塌陷或突出的部件剥离。

公开(公告)号：US07253662B2

公开(公告)日：2007-08-07

申请号：US10907957

申请日：2005-04-22

Applicant: Yu-Wen Tsai ,  Cheng-I Huang

Inventor： Yu-Wen Tsai ,  Cheng-I Huang

IPC: H03K19/00

CPC classification number: H01L27/0207 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an electric device having power switches around a logic circuit including: forming a logic circuit on a substrate; forming a plurality of power switches around the logic circuit; and coupling first ends of the power switches to a voltage end, and coupling second ends of the power switches to a power receiver of the logic circuit.

Abstract translation: 一种用于形成具有围绕逻辑电路的电源开关的电气装置的方法，包括：在基板上形成逻辑电路; 在逻辑电路周围形成多个电源开关; 并且将所述功率开关的第一端耦合到电压端，以及将所述功率开关的第二端耦合到所述逻辑电路的功率接收器。

公开(公告)号：US07165232B2

公开(公告)日：2007-01-16

申请号：US10733095

申请日：2003-12-11

Applicant: Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang ,  Ya-Yun Liu

Inventor： Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang ,  Ya-Yun Liu

IPC: G06F17/50 ,  H01L29/40

CPC classification number: H01L27/11898 ,  H01L27/0207

Abstract: An I/O circuit placement method. In the I/O circuit placement method, at least two rows of I/O circuits are placed on a first side of the chip, and each I/O circuit has a head section and a tail section. The placement direction of the head section and the tail section is perpendicular to the placement direction of the I/O circuits in the rows. The semiconductor further has a core circuit disposed on the chip, wherein the rows of I/O circuits are disposed outside the core circuit and are at the periphery of the chip. Due to the I/O circuit placement in the semiconductor device, the present invention reduces the area of the semiconductor chip and fabrication cost.

Abstract translation: 一种I / O电路放置方法。 在I / O电路放置方法中，至少两行I / O电路放置在芯片的第一侧上，并且每个I / O电路具有头部和尾部。 头部和尾部的放置方向垂直于行中的I / O电路的放置方向。 半导体还具有设置在芯片上的核心电路，其中I / O电路行设置在核心电路的外部并且位于芯片的外围。 由于半导体器件中的I / O电路布置，本发明减小了半导体芯片的面积和制造成本。

公开(公告)号：US06978411B2

公开(公告)日：2005-12-20

申请号：US10265700

申请日：2002-10-08

Applicant: Cheng-I Huang ,  Chen-Teng Fan ,  Wang-Jin Chen ,  Jyh-Herny Wang

Inventor： Cheng-I Huang ,  Chen-Teng Fan ,  Wang-Jin Chen ,  Jyh-Herny Wang

IPC: G11C29/56 ,  G01R31/28

CPC classification number: G11C29/56012 ,  G11C29/56

Abstract: A memory test system for peak power reduction. The memory test system includes a plurality of memories, a plurality of memory built-in self-test circuits and a plurality of delay units. Each of the memory built-in self-test circuits comprises a built-in self-test controller for receiving a clock signal and producing a plurality of required control signals to test one of the memories. Each of the delay units is coupled between two adjacent built-in self-test controllers. The clock signal input to one of the built-in self-test controllers is received by the delay unit to produce a delayed clock signal, and the delay unit outputs the delayed clock signal to the other.

Abstract translation: 用于峰值功率降低的记忆测试系统。 存储器测试系统包括多个存储器，多个存储器内置自检电路和多个延迟单元。 每个存储器内置的自检电路包括内置的自检控制器，用于接收时钟信号并产生多个所需的控制信号以测试其中一个存储器。 每个延迟单元耦合在两个相邻的内置自检控制器之间。 输入到内置自检控制器之一的时钟信号由延迟单元接收以产生延迟的时钟信号，并且延迟单元将延迟的时钟信号输出到另一个。