公开(公告)号：US20100237425A1

公开(公告)日：2010-09-23

申请号：US12727312

申请日：2010-03-19

申请人： Victor W.C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan ,  Roger Allen Booth, JR.

发明人： Victor W.C. Chan ,  Narasimhulu Kanike ,  Huiling Shang ,  Varadarajan Vidya ,  Jun Yuan ,  Roger Allen Booth, JR.

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823412

摘要： Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

摘要翻译： 通过选择性地去除可以用作杂质区域的外扩散阱的膜或层，形成具有不同电特性的晶体管，例如不同的开关阈值电压或不同的泄漏特性在相同的芯片或晶片上， 将诸如硼之类的杂质引入扩散槽中，使外扩散槽已经被去除时留下杂质区域基本完整。 在形成CMOS集成电路中，这种工艺允许低泄漏和低阈值晶体管的基本上最佳设计，并允许消除掩模和附加的相关工艺，特别是在使用拉伸膜来增加电子迁移率的情况下，因为拉伸膜可以 从PMOS晶体管去除拉伸膜同时从选定的NMOS晶体管中去除。

公开(公告)号：US20100207246A1

公开(公告)日：2010-08-19

申请号：US12699601

申请日：2010-02-03

申请人： Roger Allen Booth, JR. ,  Kangguo Cheng

发明人： Roger Allen Booth, JR. ,  Kangguo Cheng

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/87

摘要： A method of forming an MIM capacitor having interdigitated capacitor plates. Metal and dielectric layers are alternately deposited in an opening in a layer of insulator material. After each deposition of the metal layer, the metal layer is removed at an angle from the side to form the capacitor plate. The side from which the metal layer is removed is alternated with every metal layer that is deposited. When all the capacitor plates have been formed, the remaining opening in the layer of insulator material is filled with dielectric material then planarized, followed by the formation of contacts with the capacitor plates. There is also an MIM capacitor structure having interdigitated capacitor plates.

摘要翻译： 一种形成具有交错电容器板的MIM电容器的方法。 金属和电介质层交替沉积在绝缘体材料层的开口中。 在每次沉积金属层之后，从侧面以一角度去除金属层以形成电容器板。 去除金属层的一侧与沉积的每个金属层交替。 当所有电容器板已经形成时，绝缘体材料层中剩余的开口被电介质材料填充，然后平坦化，随后与电容器板形成接触。 还有一种具有交错电容器板的MIM电容器结构。

公开(公告)号：US20130099354A1

公开(公告)日：2013-04-25

申请号：US13279877

申请日：2011-10-24

申请人： Chengwen Pei ,  Roger Allen Booth, JR. ,  Herbert Lei Ho ,  Naoyoshi Kusaba

发明人： Chengwen Pei ,  Roger Allen Booth, JR. ,  Herbert Lei Ho ,  Naoyoshi Kusaba

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L29/945 ,  H01L29/66181

摘要： An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.

摘要翻译： 公开了一种改进的半导体电容器和制造方法。 实施例利用深沟槽，然后通过在沟槽内部执行预非晶体植入来将沟槽的内表面转变为非晶硅来处理，以消除可能降低电容器性能的耗尽区。

公开(公告)号：US20090189635A1

公开(公告)日：2009-07-30

申请号：US12020727

申请日：2008-01-28

申请人： Roger Allen Booth, JR. ,  John Richard Dangler ,  Matthew Stephen Doyle ,  Jesse Hefner ,  Thomas W. Liang ,  Ankur Kanu Patel ,  Paul W. Rudrud

发明人： Roger Allen Booth, JR. ,  John Richard Dangler ,  Matthew Stephen Doyle ,  Jesse Hefner ,  Thomas W. Liang ,  Ankur Kanu Patel ,  Paul W. Rudrud

IPC分类号： H03K19/003

CPC分类号： H03K5/084 ,  H03K5/003 ,  H03K5/151

摘要： A method and apparatus implement reduced noise coupling effects on single ended clocks, and a design structure on which the subject circuit resides is provided. A clock receiver includes a clock voltage reference that is generated from received clock peaks and valleys of a received input clock signal. The received clock peaks (VT) and the received clock valleys (VB) are continuously sampled. The clock voltage reference is set, for example, equal to an average of VT and VB; or ((VT+VB)/2).

摘要翻译： 一种方法和装置实现了对单端时钟的降低的噪声耦合效应，并且提供了主题电路所在的设计结构。 时钟接收器包括从接收到的输入时钟信号的接收时钟峰值和谷值产生的时钟参考电压。 接收的时钟峰值（VT）和接收时钟谷（VB）被连续采样。 时钟电压基准设置为例如等于VT和VB的平均值; 或（（VT + VB）/ 2）。

公开(公告)号：US20100193854A1

公开(公告)日：2010-08-05

申请号：US12692923

申请日：2010-01-25

申请人： Roger Allen Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

发明人： Roger Allen Booth, JR. ,  Kangguo Cheng ,  Chandrasekharan Kothandaraman ,  Chengwen Pei

IPC分类号： H01L29/76 ,  H01L21/335

CPC分类号： H01L29/7923 ,  H01L29/66833

摘要： Each of a hot-carrier non-volatile memory device and a method for fabricating the hot carrier non-volatile memory device is predicated upon a semiconductor structure and related method that includes a metal oxide semiconductor field effect transistor structure. The semiconductor structure and related method include at least one of: (1) a spacer that comprises a dielectric material having a dielectric constant greater than 7 (for enhanced hot carrier derived charge capture and retention); and (2) a drain region that comprises a semiconductor material that has a narrower bandgap than a bandgap of a semiconductor material from which is comprised a channel region (for enhanced impact ionization and charged carrier generation).

摘要翻译： 热载体非易失性存储器件和用于制造热载体非易失性存储器件的方法中的每一种都取决于包括金属氧化物半导体场效应晶体管结构的半导体结构和相关方法。 半导体结构和相关方法包括以下中的至少一个：（1）包括介电常数大于7的介电材料的间隔物（用于增强热载体导电的电荷捕获和保留）; 和（2）包括半导体材料的漏极区，该半导体材料具有比半导体材料的带隙窄的带隙，其包括沟道区（用于增强的冲击电离和带电载流子的生成）。

公开(公告)号：US20120119310A1

公开(公告)日：2012-05-17

申请号：US12944174

申请日：2010-11-11

申请人： Chengwen Pei ,  Roger Allen Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

发明人： Chengwen Pei ,  Roger Allen Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/49 ,  H01L21/285

CPC分类号： H01L29/49 ,  H01L21/743 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78612

摘要： A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit.

摘要翻译： 公开了一种在晶体管上制造体接触的结构和方法。 该方法包括在处理晶片上形成具有晶体管的半导体结构。 然后将结构反转，并移除手柄晶片。 然后在倒置位置的晶体管上形成硅化物体接触。 身体接触可以连接到相邻的通孔，以将身体接触连接到其他结构或水平以形成集成电路。

公开(公告)号：US20100013026A1

公开(公告)日：2010-01-21

申请号：US12173407

申请日：2008-07-15

申请人： Roger Allen Booth, JR. ,  Kangguo Cheng ,  Terence B. Hook

发明人： Roger Allen Booth, JR. ,  Kangguo Cheng ,  Terence B. Hook

IPC分类号： H01L27/02 ,  H01L21/22

CPC分类号： H01L27/0629 ,  H01L28/20

摘要： The fabrication of integrated circuits comprising resistors having the same structure but different sheet resistances is disclosed herein. In one embodiment, a method of fabricating an integrated circuit comprises: concurrently forming a first resistor laterally spaced from a second resistor above or within a semiconductor substrate, the first and second resistors comprising a doped semiconductive material; depositing a dopant receiving material across the first and second resistors and the semiconductor substrate; removing the dopant receiving material from upon the first resistor while retaining the dopant receiving material upon the second resistor; and annealing the first and second resistors to cause a first sheet resistance of the first resistor to be different from a second sheet resistance of the second resistor.

摘要翻译： 本文公开了包括具有相同结构但具有不同薄层电阻的电阻器的集成电路的制造。 在一个实施例中，一种制造集成电路的方法包括：与半导体衬底之上或之内的第二电阻器横向隔开的第一电阻器同时形成，所述第一和第二电阻器包括掺杂的半导体材料; 在第一和第二电阻器和半导体衬底上沉积掺杂剂接收材料; 在所述第一电阻器上移除所述掺杂剂接收材料，同时将所述掺杂剂接收材料保持在所述第二电阻器上; 以及使所述第一和第二电阻器退火以使所述第一电阻器的第一薄层电阻与所述第二电阻器的第二薄层电阻不同。