公开(公告)号：US06251794B1

公开(公告)日：2001-06-26

申请号：US09252627

申请日：1999-02-18

Applicant: Chiang-Jen Peng ,  Ching-Chung Lin

Inventor： Chiang-Jen Peng ,  Ching-Chung Lin

IPC: H01L21302

CPC classification number: H01L21/02063 ,  H01L21/31133 ,  H01L21/31138 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01076 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A method for removing a photoresist layer from a semiconductor substrate following a conventional dry etching step. A first wet chemical treatment strips the photoresist. A second dry ash with oxygen plasma completes the photoresist removal. To assure complete removal of photoresist imbedded on or within the material underlying the photoresist film, the semiconductor substrate is preheat treated to a temperature in the range of 150 to 250 degrees Centigrade to release the photoresist prior to the second dry ash with oxygen plasma operation. In particular, this method eliminates photoresist extrusion defects from occurring during a bond pad alloy operation.

Abstract translation: 根据常规的干蚀刻步骤，从半导体衬底去除光致抗蚀剂层的方法。 第一次湿化学处理剥离光致抗蚀剂。 具有氧等离子体的第二干灰完成光致抗蚀剂的去除。 为了确保完全去除嵌入在光致抗蚀剂膜下面的材料上的光致抗蚀剂，将半导体衬底预热处理至150至250摄氏度的温度，以在第二干灰之前用氧等离子体操作释放光致抗蚀剂。 特别地，该方法消除了在焊垫合金操作期间发生的光致抗蚀剂挤出缺陷。

公开(公告)号：US6103596A

公开(公告)日：2000-08-15

申请号：US25809

申请日：1998-02-19

Applicant: Chiang-Jen Peng

Inventor： Chiang-Jen Peng

IPC: G03F7/40 ,  H01L21/027 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L21/76202 ,  G03F7/405 ,  H01L21/0271 ,  H01L21/31144 ,  Y10S438/95

Abstract: A method for controlling the mask bias of a photoresist mask is described whereby a polymer coating is formed over the patterned photoresist mask immediately prior to etching the mask's pattern into a subjacent layer. The polymer coating is formed by treatment of the photoresist mask with a plasma, struck in within a reactive ion etching tool, in a gas mixture containing chlorine and helium. The etch durability and the thickness of the polymer coating determines the dimensional bias of the mask with respect to the pattern formed in the subjacent layer. By varying the polymer formation parameters a controllable etch bias between -0.01 and +0.03 microns can be achieved. This capability is particularly useful for patterning in integrated circuits where critical dimensions approach the resolution limits of the photolithography. The method is applied to the patterning of a silicon nitride hardmask employed in the formation of field oxide isolation (LOCOS) where a zero bias condition is achieved. The polymer coating can be formed in the same tool that is used to etch the hardmask, making the process simple and cost effective.

Abstract translation: 描述了一种用于控制光致抗蚀剂掩模的掩模偏压的方法，其中在将掩模图案蚀刻到相邻层之前立即在图案化的光致抗蚀剂掩模上形成聚合物涂层。 聚合物涂层通过用包含氯和氦的气体混合物中的等离子体处理光致抗蚀剂掩模形成，该等离子体被撞击在反应离子蚀刻工具内。 蚀刻耐久性和聚合物涂层的厚度确定掩模相对于在下层中形成的图案的尺寸偏差。 通过改变聚合物形成参数，可实现-0.01至+0.03μm之间的可控蚀刻偏压。 这种能力对于临界尺寸接近光刻分辨率极限的集成电路中的图案特别有用。 该方法适用于形成实现零偏置条件的场氧化物隔离（LOCOS）中的氮化硅硬掩模的图案化。 聚合物涂层可以与用于蚀刻硬掩模的相同工具中形成，使得该工艺简单且成本有效。

公开(公告)号：US06808589B2

公开(公告)日：2004-10-26

申请号：US10171724

申请日：2002-06-14

Applicant: Yu-Sheng Su ,  Chiang-Jen Peng ,  Pin-Chia Su ,  Wen-Lang Wu

Inventor： Yu-Sheng Su ,  Chiang-Jen Peng ,  Pin-Chia Su ,  Wen-Lang Wu

IPC: B68G6800

CPC classification number: H01L21/67259 ,  H01L21/67253 ,  H01L21/67781

Abstract: A wafer transfer robot for a wafer processing system, such as a wet bench system, and a method for utilizing the robot. The wafer transfer robot can be constructed by a robot arm that is equipped with a plurality of wafer blades each adapted for picking-up and carrying one of a plurality of wafers. The plurality of wafer blades each has a predetermined thickness, a top surface, a bottom surface and a predetermined spacing from adjacent wafer blades. A plurality of sensors, such as optical sensors, capacitance sensors or magnetic sensors, with at least one mounted on the bottom side of one of the plurality of wafer blades for sensing the presence of metal on a wafer carried on an adjacent wafer blade immediately below the one of the plurality of wafer blades.

Abstract translation: 用于晶片处理系统的晶片传送机器人，例如湿台架系统，以及利用该机器人的方法。 晶片传送机器人可以由装备有多个晶片叶片的机器人手臂构成，每个晶片叶片适于拾取和携带多个晶片中的一个。 多个晶片叶片各自具有预定的厚度，顶表面，底表面和与相邻晶片刀片的预定间隔。 多个传感器，例如光学传感器，电容传感器或磁性传感器，其中至少一个传感器安装在多个晶片刀片之一的底侧上，用于感测在紧邻下方的相邻晶片刀片上承载在晶片上的金属的存在 多个晶片刀片中的一个。

公开(公告)号：US06642150B1

公开(公告)日：2003-11-04

申请号：US09473029

申请日：1999-12-28

Applicant: Chuan-Chieh Huang ,  Wen-Hsiang Tang ,  Ming-Shuo Yen ,  Chiang-Jen Peng ,  Pei-Hung Chen

Inventor： Chuan-Chieh Huang ,  Wen-Hsiang Tang ,  Ming-Shuo Yen ,  Chiang-Jen Peng ,  Pei-Hung Chen

IPC: H01L21302

CPC classification number: H01L22/24 ,  G01N21/95692 ,  H01L22/34

Abstract: A new method for detecting blind holes in the contact layer of a multi-chip semiconductor test wafer makes use of the fact that if the hole is not a blind hole, a subsequent etch step extends the hole a predetermined distance into the layer immediately underlying the contact layer. After a predetermined number of holes have been etched through the contact layer and for a predetermined distance into the layer underlying the contact layer, the contact layer is stripped to expose the holes in the underlying layer. These holes are scanned optically by a commercial apparatus that ordinarily detects wafer defects that resemble the holes. The missing holes are detected by comparing the holes of different chips on the test wafer. The test is particularly useful with a high density plasma etch because these holes typically have a very small diameter in relation to the thickness of the contact layer.

Abstract translation: 用于检测多芯片半导体测试晶片的接触层中的盲孔的新方法利用以下事实：如果孔不是盲孔，则随后的蚀刻步骤将孔延伸到紧邻下面的层中的预定距离 接触层。 在已经通过接触层蚀刻了预定数量的孔并且进入到接触层下面的预定距离之前，剥离接触层以露出下层中的孔。 这些孔由通常检测类似于孔的晶片缺陷的商业设备进行光学扫描。 通过比较测试晶片上不同芯片的孔来检测缺失的孔。 该测试对于高密度等离子体蚀刻特别有用，因为这些孔通常相对于接触层的厚度具有非常小的直径。

公开(公告)号：US06664194B1

公开(公告)日：2003-12-16

申请号：US09270588

申请日：1999-03-18

Applicant: Dian-Hau Chen ,  Chiang-Jen Peng ,  Wei-Kay Chiu

Inventor： Dian-Hau Chen ,  Chiang-Jen Peng ,  Wei-Kay Chiu

IPC: H01L21306

CPC classification number: H01L21/0274 ,  G03F7/42 ,  G03F7/422 ,  H01L21/31138 ,  Y10S438/949

Abstract: There is first provided a substrate 10 and a target layer 12. There is then formed upon the target layer a patterned positive photoresist layer 14. There is then processed the target layer while employing the patterned positive photoresist layer as a mask layer, to thus form a processed target layer and a processed patterned positive photoresist layer. There is then photoexposed 18 the processed patterned positive photoresist layer to enhance its solubility. Finally, there is then stripped from the processed target layer the photoexposed processed patterned positive photoresist layer while employing a solvent.

Abstract translation: 首先提供衬底10和目标层12.然后在目标层上形成图案化的正性光致抗蚀剂层14.然后在使用图案化的正性光致抗蚀剂层作为掩模层的同时处理目标层，从而形成 经处理的目标层和经处理的图案化的正性光致抗蚀剂层。 然后将经处理的图案化的正性光致抗蚀剂层照射18以增强其溶解度。 最后，在使用溶剂的同时，从经处理的目标层剥离经光刻处理的图案化的正性光致抗蚀剂层。

公开(公告)号：US06660528B1

公开(公告)日：2003-12-09

申请号：US09547431

申请日：2000-04-12

Applicant: Horng-Wen Chen ,  Jeng-Fieng Lu ,  Chiang-Jen Peng

Inventor： Horng-Wen Chen ,  Jeng-Fieng Lu ,  Chiang-Jen Peng

IPC: G01N2100

CPC classification number: G01N15/06 ,  Y10T436/101666

Abstract: A method for determining the number of contaminating particles in a process chamber is described. While the method is particularly suited for detecting particles in a metal etch chamber, the present invention novel method can be utilized in any other semiconductor process chambers as long as there is a particle contamination problem. The method is carried out by conducting at least two particle dislodging cycles each including a step of flowing at least one process gas used in the process into the chamber at a flow rate of at least 30 sccm, and then evacuating the at least one process gas from the chamber to a pressure of not higher than 1 mTorr. Typical process gas that can be utilized in a metal etch chamber includes Cl2, BCl3 and Ar. The process gas should be flown into the etch chamber until a chamber pressure of at least 6 mTorr is reached, and preferably until at least a chamber pressure of 8 mTorr is reached. After the particle dislodging cycles are conducted, the number of particles that have fallen onto a top surface of the substrate can be counted by a particle counter.

Abstract translation: 描述了用于确定处理室中的污染颗粒数量的方法。 虽然该方法特别适用于检测金属蚀刻室中的颗粒，但是只要存在颗粒污染问题，本发明的新方法可用于任何其它半导体处理室。 该方法是通过进行至少两个颗粒移动循环进行的，每个颗粒移动循环包括以至少30sccm的流速将至少一种在工艺中使用的工艺气体流入室中的步骤，然后抽空至少一个工艺气体 从室到不高于1mTorr的压力。 可用于金属蚀刻室的典型工艺气体包括Cl 2，BCl 3和Ar。 工艺气体应流入蚀刻室，直到达到至少6mTorr的室压力，并且优选至少达到至少8mTorr的室压力。 在进行颗粒移动循环之后，可以通过颗粒计数器计数掉落到基板顶表面上的颗粒数。

公开(公告)号：US06500725B1

公开(公告)日：2002-12-31

申请号：US09947632

申请日：2001-09-06

Applicant: Chien-Chuan Chen ,  Chiang-Jen Peng ,  Bin-Chia Su ,  Shu-Huei Suen

Inventor： Chien-Chuan Chen ,  Chiang-Jen Peng ,  Bin-Chia Su ,  Shu-Huei Suen

IPC: H01L2176

CPC classification number: H01L23/544 ,  H01L21/76229 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed simultaneously within the substrate an alignment mark and an isolation trench formed employing a single etch method and to an identical depth within the substrate. There is then formed within the isolation trench an isolation region. Finally, there is then further processed the substrate while aligning the substrate while using the alignment mark in conjunction with a minimum of two alignment wavelengths. The method provides for enhanced efficiency when fabricating the microelectronic fabrication. The method contemplates a microelectronic fabrication fabricated employing the method.

Abstract translation: 在微电子制造的制造方法中，首先提供基板。 然后在衬底内同时形成对准标记和使用单一蚀刻方法形成的隔离沟槽，并在衬底内形成相同的深度。 然后在隔离沟槽内形成隔离区域。 最后，在使用对准标记和最少两个取向波长的同时对准衬底的同时进一步处理衬底。 该方法在制造微电子制造时提供了增强的效率。 该方法考虑使用该方法制造的微电子制造。