公开(公告)号：US20070102697A1

公开(公告)日：2007-05-10

申请号：US11164092

申请日：2005-11-10

Applicant: Fang-Chung Chen ,  Chiao-Shun Chuang

Inventor： Fang-Chung Chen ,  Chiao-Shun Chuang

IPC: H01L29/08

CPC classification number: H01L51/105 ,  H01L51/057

Abstract: A junction structure of an organic semiconductor device including an organic semiconductor layer, a conductive layer and a modifying layer is provided. The modifying layer is formed between the organic semiconductor layer and the conductive layer, wherein the modifying layer includes an inorganic compound or an organic complex compound. An organic thin film transistor including a gate, a source/drain, a dielectric layer, an organic semiconductor layer and at least a modifying layer is also provided. The gate is electrically isolated from the source/drain. The dielectric layer is disposed between the gate and the source/drain. The organic semiconductor layer is disposed between the source and the drain. The modifying layer is disposed between the organic semiconductor layer and the source/drain, wherein the modifying layer includes an inorganic compound or an organic complex compound.

Abstract translation: 提供了包括有机半导体层，导电层和改性层的有机半导体器件的结结构。 在有机半导体层和导电层之间形成改性层，其中改性层包括无机化合物或有机络合物。 还提供了包括栅极，源极/漏极，电介质层，有机半导体层和至少改性层的有机薄膜晶体管。 栅极与源极/漏极电隔离。 电介质层设置在栅极和源极/漏极之间。 有机半导体层设置在源极和漏极之间。 改性层设置在有机半导体层和源极/漏极之间，其中改性层包括无机化合物或有机络合物。

公开(公告)号：US20090039448A1

公开(公告)日：2009-02-12

申请号：US11924615

申请日：2007-10-26

Applicant: Chiao-Shun Chuang ,  Fang-Chung Chen ,  Han-Ping David Shieh

Inventor： Chiao-Shun Chuang ,  Fang-Chung Chen ,  Han-Ping David Shieh

IPC: H01L31/02

CPC classification number: G02F1/133514 ,  G02F1/133345 ,  G02F1/133617 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2202/046 ,  G02F2202/36

Abstract: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a semi-conductive layer, a gate insulator, a source and a drain. The gate insulator is located between the gate and the semi-conductive layer. A light shows a specific color after passing through the gate insulator. The source and the drain are disposed on the semi-conductive layer. A pixel structure and a liquid crystal display panel having the pixel structure are also provided. The liquid crystal display panel can display colorful images without disposing a color filter array additionally so that the manufacturing process of the liquid crystal panel is simple and the manufacturing cost of the liquid crystal panel is low.

Abstract translation: 设置在基板上的薄膜晶体管。 薄膜晶体管包括栅极，半导电层，栅极绝缘体，源极和漏极。 栅极绝缘体位于栅极和半导体层之间。 光通过栅极绝缘体后显示特定的颜色。 源极和漏极设置在半导体层上。 还提供了具有像素结构的像素结构和液晶显示面板。 液晶显示面板可以在不附加滤色器阵列的情况下显示彩色图像，使得液晶面板的制造过程简单，并且液晶面板的制造成本低。

公开(公告)号：US20070158647A1

公开(公告)日：2007-07-12

申请号：US11467165

申请日：2006-08-25

Applicant: Fang-Chung Chen ,  Chiao-Shun Chuang ,  Dong-Sian Chen ,  Li-Jen Kung ,  Yung-Sheng Lin ,  Chuan-Yi Wu

Inventor： Fang-Chung Chen ,  Chiao-Shun Chuang ,  Dong-Sian Chen ,  Li-Jen Kung ,  Yung-Sheng Lin ,  Chuan-Yi Wu

IPC: H01L29/08 ,  H01L35/24 ,  H01L51/00

CPC classification number: H01L51/105 ,  H01L51/057

Abstract: A junction structure of an organic semiconductor device including an organic semiconductor layer, a conductive layer and a modifying layer is provided. The modifying layer is formed between the organic semiconductor layer and the conductive layer, wherein the modifying layer includes an inorganic compound or an organic complex compound. An organic thin film transistor including a gate, a source/drain, a dielectric layer, an organic semiconductor layer and at least a modifying layer is also provided. The gate is electrically isolated from the source/drain. The dielectric layer is disposed between the gate and the source/drain. The organic semiconductor layer is disposed between the source and the drain. The modifying layer is disposed between the organic semiconductor layer and the source/drain, wherein the modifying layer includes an inorganic compound or an organic complex compound.

公开(公告)号：US08907325B2

公开(公告)日：2014-12-09

申请号：US11924615

申请日：2007-10-26

Applicant: Chiao-Shun Chuang ,  Fang-Chung Chen ,  Han-Ping David Shieh

Inventor： Chiao-Shun Chuang ,  Fang-Chung Chen ,  Han-Ping David Shieh

IPC: H01L29/08 ,  H01L35/24 ,  H01L29/10 ,  G02F1/1335 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: G02F1/133514 ,  G02F1/133345 ,  G02F1/133617 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2202/046 ,  G02F2202/36

Abstract: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a semi-conductive layer, a gate insulator, a source and a drain. The gate insulator is located between the gate and the semi-conductive layer. A light shows a specific color after passing through the gate insulator. The source and the drain are disposed on the semi-conductive layer. A pixel structure and a liquid crystal display panel having the pixel structure are also provided. The liquid crystal display panel can display colorful images without disposing a color filter array additionally so that the manufacturing process of the liquid crystal panel is simple and the manufacturing cost of the liquid crystal panel is low.

Abstract translation: 设置在基板上的薄膜晶体管。 薄膜晶体管包括栅极，半导电层，栅极绝缘体，源极和漏极。 栅极绝缘体位于栅极和半导体层之间。 光通过栅极绝缘体后显示特定的颜色。 源极和漏极设置在半导体层上。 还提供了具有像素结构的像素结构和液晶显示面板。 液晶显示面板可以在不附加滤色器阵列的情况下显示彩色图像，使得液晶面板的制造过程简单，并且液晶面板的制造成本低。

公开(公告)号：US20070215957A1

公开(公告)日：2007-09-20

申请号：US11459409

申请日：2006-07-24

Applicant: Fang-Chung Chen ,  Chiao-Shun Chuang ,  Yung-Sheng Lin

Inventor： Fang-Chung Chen ,  Chiao-Shun Chuang ,  Yung-Sheng Lin

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC classification number: H01L51/0537 ,  H01L51/0529

Abstract: A gate dielectric structure and an organic thin film transistor based thereon, wherein the gate dielectric structure comprises: an organic-inorganic composite layer and an organic insulation layer, and the gate dielectric structure is applied to an organic thin film transistor. As the organic-inorganic composite layer of the gate dielectric structure has an organic insulation matrix blended with inorganic surface-modified particles, it can achieve a high dielectric constant. Further, as the organic insulation layer can modify the surface of the organic-inorganic composite layer, not only the leakage current is reduced, but also the crystalline structure of the organic semiconductor layer becomes more orderly. Thus, the carrier mobility is raised, the current output of the element is increased, and the performance of the element is also greatly enhanced.

Abstract translation: 一种栅极电介质结构和基于其的有机薄膜晶体管，其中所述栅极介电结构包括：有机 - 无机复合层和有机绝缘层，并且所述栅极电介质结构被施加到有机薄膜晶体管。 由于栅极电介质结构的有机 - 无机复合层具有与无机表面改性粒子混合的有机绝缘基体，因此可以实现高介电常数。 此外，由于有机绝缘层可以改变有机 - 无机复合层的表面，不仅漏电流降低，而且有机半导体层的晶体结构变得更有序。 因此，载流子迁移率提高，元件的电流输出增加，元件的性能也大大提高。

公开(公告)号：US07087958B2

公开(公告)日：2006-08-08

申请号：US10771957

申请日：2004-02-03

Applicant: Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Hsing-Huang Hsieh

Inventor： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Hsing-Huang Hsieh

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7811 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7813

Abstract: In one embodiment of the invention, a semiconductor device set includes at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and includes a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer. The trench-typed termination structure has a trench profile and includes an oxide layer in the trench profile. A termination polysilicon layer with discrete features separates the termination polysilicon layer. An isolation layer covers the termination polysilicon layer and filling the discrete features. The trench-typed MOSFET and the trench-typed termination structure may be formed on a DMOS device including an N+ silicon substrate, an N epitaxial layer on the N+ silicon substrate, and a P epitaxial layer on the N epitaxial layer. The trench profiles of the trench-typed MOSFET and of the trench-typed termination structure may penetrate through the P epitaxial layer into the N epitaxial layer.

Abstract translation: 在本发明的一个实施例中，半导体器件组包括至少一个沟槽型MOSFET和沟槽型端接结构。 沟槽型MOSFET具有沟槽轮廓并且在沟槽轮廓中包括栅极氧化物层，并且在栅极氧化物层上包括多晶硅层。 沟槽式端接结构具有沟槽轮廓并且在沟槽轮廓中包括氧化物层。 具有离散特征的端接多晶硅层分离端接多晶硅层。 隔离层覆盖终端多晶硅层并填充离散特征。 沟槽型MOSFET和沟槽型端接结构可以形成在包括N +硅衬底，N +硅衬底上的N外延层和N外延层上的P外延层的DMOS器件上。 沟槽型MOSFET和沟槽型端接结构的沟槽轮廓可以穿透P外延层进入N外延层。

公开(公告)号：US06677223B2

公开(公告)日：2004-01-13

申请号：US10219092

申请日：2002-08-13

Applicant: Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Hsin-Huang Hsieh

Inventor： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Hsin-Huang Hsieh

IPC: H01L2120

CPC classification number: H01L21/28167

Abstract: Embodiments of the present invention relate to processes utilized in the manufacturing of a semiconductor device having transistors to achieve high uniformity of threshold voltages. The invention does so by ensuring high uniformity of impurity concentration in the substrate. In one embodiment, a method for manufacturing a semiconductor device having transistors with high uniformity of threshold voltages comprises providing a substrate and a source of impurities, and disposing the substrate and the source of impurities in a first oxygen gas at a first initial temperature and heated to a first target temperature at a first temperature rate to drive the impurities into the substrate. The first initial temperature is sufficiently low to prevent the oxygen from diffusing into the substrate. The substrate is disposed in a second oxygen gas at a second initial temperature and heated to a second target temperature at a second rate to form an oxide layer on the substrate. The second rate is high enough for rapid formation of the oxide layer on the substrate so as to prevent the impurities driven into the substrate from diffusing out from the substrate.

Abstract translation: 本发明的实施例涉及用于制造具有晶体管以实现阈值电压的高均匀性的半导体器件的工艺。 本发明通过确保衬底中杂质浓度的高均匀性来实现。 在一个实施例中，制造具有高阈值电压均匀性的晶体管的半导体器件的方法包括提供衬底和杂质源，并将衬底和杂质源置于第一初始温度的第一氧气中并加热 以第一温度速率升至第一目标温度以驱动杂质进入基板。 第一初始温度足够低以防止氧扩散到基底中。 将衬底在第二初始温度下设置在第二氧气中，并以第二速率加热至第二目标温度，以在衬底上形成氧化物层。 第二速率足够高以快速形成衬底上的氧化物层，以防止驱动到衬底中的杂质从衬底扩散出来。

公开(公告)号：US08368140B2

公开(公告)日：2013-02-05

申请号：US12630088

申请日：2009-12-03

Applicant: Chiao-Shun Chuang

Inventor： Chiao-Shun Chuang

IPC: H01L29/66

CPC classification number: H01L29/7827 ,  H01L27/0727

Abstract: In one embodiment the present invention includes a semiconductor device. The semiconductor device comprises a first semiconductor region, a second semiconductor region and a trench region. The first semiconductor region is of a first conductivity type and a first conductivity concentration. The trench region includes a metal layer in contact with the first semiconductor region to form a metal-semiconductor junction. The second semiconductor region is adjacent to the first semiconductor region that has a second conductivity type and a second conductivity concentration. The second semiconductor region forms a PN junction with the first semiconductor region, and the trench region has a depth such that the metal-semiconductor junction is proximate to the PN junction.

Abstract translation: 在一个实施例中，本发明包括半导体器件。 半导体器件包括第一半导体区域，第二半导体区域和沟槽区域。 第一半导体区域是第一导电类型和第一电导率浓度。 沟槽区域包括与第一半导体区域接触以形成金属 - 半导体结的金属层。 第二半导体区域与具有第二导电类型和第二电导率浓度的第一半导体区域相邻。 第二半导体区域与第一半导体区域形成PN结，并且沟槽区域具有使得金属 - 半导体结接近PN结的深度。

公开(公告)号：US06989306B2

公开(公告)日：2006-01-24

申请号：US10771808

申请日：2004-02-03

Applicant: Chiao-Shun Chuang ,  Hsin-Huang Hsieh ,  Mao-Song Tseng ,  Chien-Ping Chang

Inventor： Chiao-Shun Chuang ,  Hsin-Huang Hsieh ,  Mao-Song Tseng ,  Chien-Ping Chang

IPC: H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7813

Abstract: Embodiments of the invention provide a termination structure of DMOS device and a method of forming the same. In forming the termination structure, a silicon substrate with an epitaxial layer formed thereon is provided. A body region defined by doping the epitaxial layer is then selectively etched to form a plurality of DMOS trenches therein. Thereafter, a gate oxide layer is formed over exposed surfaces in the body region and a termination oxide layer is formed to encircle the body region. Afterward, a polysilicon layer is deposited over all the exposed surfaces, and then selectively etched to form a plurality of poly gates in the DMOS trenches and a polysilicon plate having an extending portion toward the body region over the termination oxide layer. By using the termination polysilicon layer as an implantation mask, sources are formed in the body region. Afterward, an isolation layer and a source metal contact layer are deposited over the structure, in which the isolation layer is utilized to protect the polysilicon gates, and also the source metal contact layer is utilized to ground both the body region and the polysilicon plate.

Abstract translation: 本发明的实施例提供了一种DMOS器件的端接结构及其形成方法。 在形成端接结构时，提供其上形成有外延层的硅衬底。 然后选择性地蚀刻通过掺杂外延层限定的体区，以在其中形成多个DMOS沟槽。 此后，在体区域中的暴露表面上形成栅极氧化物层，并且形成终止氧化物层以环绕身体区域。 之后，在所有暴露的表面上沉积多晶硅层，然后选择性地蚀刻以在DMOS沟槽中形成多个多晶硅栅极，以及在端接氧化物层上具有朝向主体区域的延伸部分的多晶硅板。 通过使用终止多晶硅层作为注入掩模，在体区域中形成源。 之后，在结构上沉积隔离层和源极金属接触层，其中隔离层用于保护多晶硅栅极，并且源极金属接触层用于接地体区域和多晶硅板。

公开(公告)号：US20050199952A1

公开(公告)日：2005-09-15

申请号：US11056450

申请日：2005-02-11

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L31/119

CPC classification number: H01L29/7813 ,  H01L29/0661 ,  H01L29/41766 ,  H01L29/7802

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench. A metal layer covers portions of the passivation layer on the side walls of the trench to expose a part of the passivation layer over the bottom surface of the trench.