公开(公告)号：US20090026516A1

公开(公告)日：2009-01-29

申请号：US11951270

申请日：2007-12-05

申请人： Chien-Li CHENG ,  Shian-Jyh Lin ,  Ming-Yuan Huang

发明人： Chien-Li CHENG ,  Shian-Jyh Lin ,  Ming-Yuan Huang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10867

摘要： A method for fabricating a semiconductor memory device. A pair of neighboring trench capacitors is formed in a substrate. An insulating layer having a pair of connecting structures therein is formed on the substrate, in which the pair of connecting structures is electrically connected to the pair of neighboring trench capacitors. An active layer is formed on the insulating layer between the pair of connecting structures so as to cover the pair of connecting structures. A pair of gate structures is formed on the active layer to electrically connect to the pair of trench capacitors. A semiconductor memory device is also disclosed.

摘要翻译： 一种制造半导体存储器件的方法。 在衬底中形成一对相邻的沟槽电容器。 在其上形成有一对连接结构的绝缘层，其中一对连接结构电连接到一对相邻的沟槽电容器。 在一对连接结构之间的绝缘层上形成有源层，以便覆盖该对连接结构。 在有源层上形成一对栅极结构，以电连接到该对沟槽电容器。 还公开了一种半导体存储器件。

公开(公告)号：US07638391B2

公开(公告)日：2009-12-29

申请号：US11951270

申请日：2007-12-05

申请人： Chien-Li Cheng ,  Shian-Jyh Lin ,  Ming-Yuan Huang

发明人： Chien-Li Cheng ,  Shian-Jyh Lin ,  Ming-Yuan Huang

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10867

摘要： A method for fabricating a semiconductor memory device. A pair of neighboring trench capacitors is formed in a substrate. An insulating layer having a pair of connecting structures therein is formed on the substrate, in which the pair of connecting structures is electrically connected to the pair of neighboring trench capacitors. An active layer is formed on the insulating layer between the pair of connecting structures so as to cover the pair of connecting structures. A pair of gate structures is formed on the active layer to electrically connect to the pair of trench capacitors. A semiconductor memory device is also disclosed.

摘要翻译： 一种制造半导体存储器件的方法。 在衬底中形成一对相邻的沟槽电容器。 在其上形成有一对连接结构的绝缘层，其中一对连接结构电连接到该对相邻的沟槽电容器。 在一对连接结构之间的绝缘层上形成有源层，以便覆盖该对连接结构。 在有源层上形成一对栅极结构，以电连接到该对沟槽电容器。 还公开了一种半导体存储器件。

公开(公告)号：US20090008692A1

公开(公告)日：2009-01-08

申请号：US11966891

申请日：2007-12-28

申请人： Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

发明人： Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10876 ,  H01L27/10894

摘要： A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.

摘要翻译： 半导体器件包括半导体衬底。 半导体衬底具有存储器阵列区域和外围电路区域; 外围电路区域中的第一有源区和第二有源区; 设置在所述存储器阵列区域上的凹入栅极，包括在所述半导体衬底上的第一栅极介电层，其中所述第一栅极介电层具有第一厚度; 以及在所述外围电路区上的第二栅介质层，其中所述第一有源层上的所述第二栅介质层具有第二厚度，并且所述第二有源层上的所述第二栅介质层具有第三厚度。

公开(公告)号：US07622381B2

公开(公告)日：2009-11-24

申请号：US11829371

申请日：2007-07-27

申请人： Jar-Ming Ho ,  Shian-Jyh Lin ,  Ming-Yuan Huang

发明人： Jar-Ming Ho ,  Shian-Jyh Lin ,  Ming-Yuan Huang

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/76834 ,  H01L27/10888 ,  H01L27/10894

摘要： The present invention provides a semiconductor structure and the forming method thereof. The structure includes a substrate having a plurality of stacks; a conformal layer on the substrate and a portion of sidewalls of the plurality of the stacks; and a plurality of plugs between the plurality of stacks. In addition, the present invention also provides a method of forming the semiconductor structure, comprising steps of providing a substrate; forming a plurality of stacks on the substrate; forming a conformal layer on the stacks and on the substrate; removing a portion of the conformal layer to expose a sidewall and a top surface of the plurality of stacks; and forming a plurality of plugs between the stacks.

摘要翻译： 本发明提供一种半导体结构及其形成方法。 该结构包括具有多个堆叠的基板; 所述衬底上的共形层和所述多个所述堆叠中的侧壁的一部分; 以及多个堆叠之间的多个插头。 此外，本发明还提供一种形成半导体结构的方法，包括提供衬底的步骤; 在所述基板上形成多个堆叠; 在堆叠和基板上形成共形层; 去除所述共形层的一部分以暴露所述多个叠层的侧壁和顶表面; 以及在所述堆叠之间形成多个塞子。

公开(公告)号：US20080217779A1

公开(公告)日：2008-09-11

申请号：US11829371

申请日：2007-07-27

申请人： Jar-Ming Ho ,  Shian-Jyh Lin ,  Ming-Yuan Huang

发明人： Jar-Ming Ho ,  Shian-Jyh Lin ,  Ming-Yuan Huang

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76897 ,  H01L21/76834 ,  H01L27/10888 ,  H01L27/10894

摘要： The present invention provides a semiconductor structure and the forming method thereof. The structure includes a substrate having a plurality of stacks; a conformal layer on the substrate and a portion of sidewalls of the plurality of the stacks; and a plurality of plugs between the plurality of stacks. In addition, the present invention also provides a method of forming the semiconductor structure, comprising steps of providing a substrate; forming a plurality of stacks on the substrate; forming a conformal layer on the stacks and on the substrate; removing a portion of the conformal layer to expose a sidewall and a top surface of the plurality of stacks; and forming a plurality of plugs between the stacks.

摘要翻译： 本发明提供一种半导体结构及其形成方法。 该结构包括具有多个堆叠的基板; 所述衬底上的共形层和所述多个所述堆叠中的侧壁的一部分; 以及多个堆叠之间的多个插头。 此外，本发明还提供一种形成半导体结构的方法，包括提供衬底的步骤; 在所述基板上形成多个堆叠; 在堆叠和基板上形成共形层; 去除所述共形层的一部分以暴露所述多个叠层的侧壁和顶表面; 以及在所述堆叠之间形成多个塞子。

公开(公告)号：US07955927B2

公开(公告)日：2011-06-07

申请号：US11966891

申请日：2007-12-28

申请人： Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

发明人： Shian-Jyh Lin ,  Yu-Pi Lee ,  Ming-Yuan Huang ,  Jar-Ming Ho ,  Shun-Fu Chen ,  Tse-Chuan Kuo

IPC分类号： H01L21/8242

CPC分类号： H01L27/10876 ,  H01L27/10894

摘要： A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.

摘要翻译： 半导体器件包括半导体衬底。 半导体衬底具有存储器阵列区域和外围电路区域; 外围电路区域中的第一有源区和第二有源区; 设置在所述存储器阵列区域上的凹入栅极，包括在所述半导体衬底上的第一栅极介电层，其中所述第一栅极介电层具有第一厚度; 以及在所述外围电路区上的第二栅介质层，其中所述第一有源层上的所述第二栅介质层具有第二厚度，并且所述第二有源层上的所述第二栅介质层具有第三厚度。

公开(公告)号：US07619271B2

公开(公告)日：2009-11-17

申请号：US11940547

申请日：2007-11-15

申请人： Shian-Jyh Lin ,  Chien-Li Cheng

发明人： Shian-Jyh Lin ,  Chien-Li Cheng

IPC分类号： H01L29/94

CPC分类号： H01L29/945 ,  H01L27/10823 ,  H01L27/10867 ,  H01L29/66181

摘要： A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed.

摘要翻译： 具有单面连接结构的深沟槽装置。 该装置包括其中具有沟槽的衬底。 埋沟槽电容器设置在沟槽的下部。 不对称环形绝缘体设置在沟槽的侧壁的上部。 连接结构设置在沟槽的上部，包括设置在不对称环形绝缘体的相对较低部分上并与其相邻的外延硅层，以及设置在外延硅层和不对称的较高部分之间的连接构件 项圈绝缘子。 导电层设置在不对称环形绝缘体的相对较高和较低的部分之间，以电连接埋入沟槽电容器和连接结构。 盖层设置在连接结构上。 还公开了一种深沟槽器件的制造方法。

公开(公告)号：US20070246755A1

公开(公告)日：2007-10-25

申请号：US11696163

申请日：2007-04-03

申请人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

发明人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L27/10861 ,  H01L27/0629 ,  H01L27/10876

摘要： A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

摘要翻译： 公开了一种使用TTO多隔离件制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。 聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

公开(公告)号：US07446355B2

公开(公告)日：2008-11-04

申请号：US11556170

申请日：2006-11-03

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/66553 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66621 ,  H01L29/66659

摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

摘要翻译： 公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。 提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。 多个沟槽嵌入在半导体衬底的存储器阵列区域中。 每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。 非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

公开(公告)号：US07795090B2

公开(公告)日：2010-09-14

申请号：US12211815

申请日：2008-09-17

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

IPC分类号： H01L21/8242

CPC分类号： H01L29/66553 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66621 ,  H01L29/66659

摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

摘要翻译： 公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。 提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。 多个沟槽嵌入在半导体衬底的存储器阵列区域中。 每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。 非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。