公开(公告)号：US07897501B2

公开(公告)日：2011-03-01

申请号：US12013528

申请日：2008-01-14

申请人： Chien-Li Cheng ,  Sun-Jay Chang ,  Tung-Heng Hsieh ,  Yung-Shen Chen

发明人： Chien-Li Cheng ,  Sun-Jay Chang ,  Tung-Heng Hsieh ,  Yung-Shen Chen

IPC分类号： H01L21/4763

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.

摘要翻译： 公开了制造半导体器件的方法。 制造半导体器件的方法提供半导体衬底; 形成覆盖在半导体衬底上的栅叠层; 每个在所述栅极叠层的侧壁上具有第一内隔离物和第二外隔离物的隔离物; 在所述间隔物的侧壁上形成保护层，覆盖所述半导体衬底的一部分，其中所述保护层的蚀刻选择性高于所述第一内衬垫的蚀刻选择性。

公开(公告)号：US20080268602A1

公开(公告)日：2008-10-30

申请号：US12013528

申请日：2008-01-14

申请人： Chien-Li Cheng ,  Sun-Jay Chang ,  Tung-Heng Hsieh ,  Yung-Shun Chen

发明人： Chien-Li Cheng ,  Sun-Jay Chang ,  Tung-Heng Hsieh ,  Yung-Shun Chen

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.

摘要翻译： 公开了制造半导体器件的方法。 制造半导体器件的方法提供半导体衬底; 形成覆盖在半导体衬底上的栅叠层; 每个在所述栅极叠层的侧壁上具有第一内隔离物和第二外隔离物的隔离物; 在所述间隔物的侧壁上形成保护层，覆盖所述半导体衬底的一部分，其中所述保护层的蚀刻选择性高于所述第一内衬垫的蚀刻选择性。

公开(公告)号：US20060231910A1

公开(公告)日：2006-10-19

申请号：US11107625

申请日：2005-04-15

申请人： Tung-Heng Hsieh ,  Chien-Li Cheng ,  Yi-Shien Mor ,  Yung-Shun Chen

发明人： Tung-Heng Hsieh ,  Chien-Li Cheng ,  Yi-Shien Mor ,  Yung-Shun Chen

IPC分类号： H01L29/78 ,  H01L21/44

CPC分类号： H01L21/28052 ,  H01L29/665 ,  H01L29/6659

摘要： A method for forming silicide and a semiconductor device formed thereby. A Si-containing polycrystalline region is converted to an amorphous region, and annealed to form a regrown polycrystalline region having an increased grain size. A silicide layer is formed by reacting a metal and the regrown polycrystalline region having the increased grain size.

摘要翻译： 一种形成硅化物的方法和由此形成的半导体器件。 将含Si的多晶区域转变为非晶区域，并退火以形成具有增加的晶粒尺寸的再生长多晶区域。 通过金属和具有增加的晶粒尺寸的再结晶多晶区域的反应形成硅化物层。

公开(公告)号：US07382028B2

公开(公告)日：2008-06-03

申请号：US11107625

申请日：2005-04-15

申请人： Tung-Heng Hsieh ,  Chien-Li Cheng ,  Yi-Shien Mor ,  Yung-Shun Chen

发明人： Tung-Heng Hsieh ,  Chien-Li Cheng ,  Yi-Shien Mor ,  Yung-Shun Chen

IPC分类号： H01L29/423

CPC分类号： H01L21/28052 ,  H01L29/665 ,  H01L29/6659

摘要： A method for forming silicide and a semiconductor device formed thereby. A Si-containing polycrystalline region is converted to an amorphous region, and annealed to form a regrown polycrystalline region having an increased grain size. A silicide layer is formed by reacting a metal and the regrown polycrystalline region having the increased grain size.

摘要翻译： 一种形成硅化物的方法和由此形成的半导体器件。 将含Si的多晶区域转变为非晶区域，并退火以形成具有增加的晶粒尺寸的再生长多晶区域。 通过金属和具有增加的晶粒尺寸的再结晶多晶区域的反应形成硅化物层。

公开(公告)号：US07190033B2

公开(公告)日：2007-03-13

申请号：US10826956

申请日：2004-04-15

申请人： Sun-Jay Chang ,  Chien-Li Cheng

发明人： Sun-Jay Chang ,  Chien-Li Cheng

IPC分类号： H01L29/76

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/7843

摘要： A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer is disposed between the source or drain region of the PMOS transistor and an overlying surface tension-inducing layer. The surface tension-inducing layer may comprise a nitride material or carbon-containing material, and the surface tension-reducing layer may comprise an oxide material. Degradation of hole mobility in the PMOS transistor is prevented by the use of the surface tension-reducing layer of the bilayer etch stop.

摘要翻译： 一种CMOS器件及其制造方法，其中在PMOS晶体管上使用双层蚀刻停止，并且单个蚀刻停止层用于NMOS晶体管，用于形成到CMOS器件的源极或漏极的触点。 表面张力降低层设置在PMOS晶体管的源极或漏极区域和上覆表面张力诱导层之间。 表面张力诱导层可以包括氮化物材料或含碳材料，并且表面张力减小层可以包括氧化物材料。 通过使用双层蚀刻停止层的表面张力降低层来防止PMOS晶体管中空穴迁移率的降低。

公开(公告)号：US20050230756A1

公开(公告)日：2005-10-20

申请号：US10826956

申请日：2004-04-15

申请人： Sun-Jay Chang ,  Chien-Li Cheng

发明人： Sun-Jay Chang ,  Chien-Li Cheng

IPC分类号： H01L21/8238 ,  H01L27/01

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/7843

摘要： A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer is disposed between the source or drain region of the PMOS transistor and an overlying surface tension-inducing layer. The surface tension-inducing layer may comprise a nitride material or carbon-containing material, and the surface tension-reducing layer may comprise an oxide material. Degradation of hole mobility in the PMOS transistor is prevented by the use of the surface tension-reducing layer of the bilayer etch stop.

摘要翻译： 一种CMOS器件及其制造方法，其中在PMOS晶体管上使用双层蚀刻停止，并且单个蚀刻停止层用于NMOS晶体管，用于形成到CMOS器件的源极或漏极的触点。 表面张力降低层设置在PMOS晶体管的源极或漏极区域和上覆表面张力诱导层之间。 表面张力诱导层可以包括氮化物材料或含碳材料，并且表面张力减小层可以包括氧化物材料。 通过使用双层蚀刻停止层的表面张力降低层来防止PMOS晶体管中空穴迁移率的降低。

公开(公告)号：US20100012179A1

公开(公告)日：2010-01-21

申请号：US12372975

申请日：2009-02-18

申请人： Chien-Li Cheng

发明人： Chien-Li Cheng

IPC分类号： H01L31/00 ,  H01L21/3105 ,  H01L21/02

CPC分类号： H01L31/022425 ,  H01L31/02168 ,  H01L31/022466 ,  Y02E10/50

摘要： A solar cell with high photon utilization includes a substrate, a transparent conductive oxide layer, an anti-reflection coating (ARC) layer and at least one main charge collecting line. The substrate has a front side and a back side. The substrate has a first-type semiconductor layer close to the back side and a second-type semiconductor layer close to the front side. The transparent conductive oxide layer is formed on the front side. The ARC layer is formed on the transparent conductive oxide layer. The main charge collecting line penetrates through the ARC layer and projects from the ARC layer, and the main charge collecting line is electrically connected to the transparent conductive oxide layer. A method of manufacturing the solar cell is also disclosed.

摘要翻译： 具有高光子利用率的太阳能电池包括基板，透明导电氧化物层，抗反射涂层（ARC）层和至少一个主电荷收集线。 基板具有前侧和后侧。 衬底具有靠近背面的第一类型半导体层和靠近正面的第二类型半导体层。 透明导电氧化物层形成在前侧。 ARC层形成在透明导电氧化物层上。 主电荷收集线穿过ARC层并从ARC层突出，并且主电荷收集线电连接到透明导电氧化物层。 还公开了一种制造太阳能电池的方法。

公开(公告)号：US20070190712A1

公开(公告)日：2007-08-16

申请号：US11521639

申请日：2006-09-14

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Chung-Yuan Lee ,  Jeng-Ping Lin ,  Pei-Ing Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Chung-Yuan Lee ,  Jeng-Ping Lin ,  Pei-Ing Lee

IPC分类号： H01L21/8234

CPC分类号： H01L29/42376 ,  H01L29/66621

摘要： A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a trench having a sidewall and a bottom using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the trench to form a doped region. The semiconductor substrate underlying the trench is etched to form an extended portion. A gate insulating layer is formed on the trench and the extended portion. A trench gate is formed in the trench and the extended portion.

摘要翻译： 提供一种制造具有沟槽栅极的半导体器件的方法。 首先，提供其上具有沟槽蚀刻掩模的半导体衬底。 使用沟槽蚀刻掩模作为屏蔽，蚀刻半导体衬底以形成具有侧壁和底部的沟槽。 杂质通过沟槽掺杂到半导体衬底中以形成掺杂区域。 蚀刻沟槽下方的半导体衬底以形成延伸部分。 在沟槽和延伸部分上形成栅极绝缘层。 在沟槽和延伸部分中形成沟槽栅极。

公开(公告)号：US07619271B2

公开(公告)日：2009-11-17

申请号：US11940547

申请日：2007-11-15

申请人： Shian-Jyh Lin ,  Chien-Li Cheng

发明人： Shian-Jyh Lin ,  Chien-Li Cheng

IPC分类号： H01L29/94

CPC分类号： H01L29/945 ,  H01L27/10823 ,  H01L27/10867 ,  H01L29/66181

摘要： A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed.

摘要翻译： 具有单面连接结构的深沟槽装置。 该装置包括其中具有沟槽的衬底。 埋沟槽电容器设置在沟槽的下部。 不对称环形绝缘体设置在沟槽的侧壁的上部。 连接结构设置在沟槽的上部，包括设置在不对称环形绝缘体的相对较低部分上并与其相邻的外延硅层，以及设置在外延硅层和不对称的较高部分之间的连接构件 项圈绝缘子。 导电层设置在不对称环形绝缘体的相对较高和较低的部分之间，以电连接埋入沟槽电容器和连接结构。 盖层设置在连接结构上。 还公开了一种深沟槽器件的制造方法。

公开(公告)号：US20080009112A1

公开(公告)日：2008-01-10

申请号：US11858703

申请日：2007-09-20

申请人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

发明人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

IPC分类号： H01L21/8242

CPC分类号： H01L29/66621 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10876

摘要： A method for forming a semiconductor memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.

摘要翻译： 公开了一种用于形成具有凹入栅极的半导体存储器件的方法。 提供其上具有垫层的衬底。 图案化衬垫层和衬底以形成至少两个沟槽。 在每个沟槽中形成深沟槽电容器。 在每个深沟槽电容器上形成突起，其中每个突起的顶表面水平高于焊盘层的顶表面高度。 间隔件形成在突起的侧壁上，并且使用间隔件和突起作为掩模来蚀刻衬垫层和衬底以形成凹部。 在凹部中形成凹槽。