公开(公告)号：US07897501B2

公开(公告)日：2011-03-01

申请号：US12013528

申请日：2008-01-14

申请人： Chien-Li Cheng ,  Sun-Jay Chang ,  Tung-Heng Hsieh ,  Yung-Shen Chen

发明人： Chien-Li Cheng ,  Sun-Jay Chang ,  Tung-Heng Hsieh ,  Yung-Shen Chen

IPC分类号： H01L21/4763

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.

摘要翻译： 公开了制造半导体器件的方法。 制造半导体器件的方法提供半导体衬底; 形成覆盖在半导体衬底上的栅叠层; 每个在所述栅极叠层的侧壁上具有第一内隔离物和第二外隔离物的隔离物; 在所述间隔物的侧壁上形成保护层，覆盖所述半导体衬底的一部分，其中所述保护层的蚀刻选择性高于所述第一内衬垫的蚀刻选择性。

公开(公告)号：US20080268602A1

公开(公告)日：2008-10-30

申请号：US12013528

申请日：2008-01-14

申请人： Chien-Li Cheng ,  Sun-Jay Chang ,  Tung-Heng Hsieh ,  Yung-Shun Chen

发明人： Chien-Li Cheng ,  Sun-Jay Chang ,  Tung-Heng Hsieh ,  Yung-Shun Chen

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.

摘要翻译： 公开了制造半导体器件的方法。 制造半导体器件的方法提供半导体衬底; 形成覆盖在半导体衬底上的栅叠层; 每个在所述栅极叠层的侧壁上具有第一内隔离物和第二外隔离物的隔离物; 在所述间隔物的侧壁上形成保护层，覆盖所述半导体衬底的一部分，其中所述保护层的蚀刻选择性高于所述第一内衬垫的蚀刻选择性。

公开(公告)号：US20050230756A1

公开(公告)日：2005-10-20

申请号：US10826956

申请日：2004-04-15

申请人： Sun-Jay Chang ,  Chien-Li Cheng

发明人： Sun-Jay Chang ,  Chien-Li Cheng

IPC分类号： H01L21/8238 ,  H01L27/01

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/7843

摘要： A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer is disposed between the source or drain region of the PMOS transistor and an overlying surface tension-inducing layer. The surface tension-inducing layer may comprise a nitride material or carbon-containing material, and the surface tension-reducing layer may comprise an oxide material. Degradation of hole mobility in the PMOS transistor is prevented by the use of the surface tension-reducing layer of the bilayer etch stop.

摘要翻译： 一种CMOS器件及其制造方法，其中在PMOS晶体管上使用双层蚀刻停止，并且单个蚀刻停止层用于NMOS晶体管，用于形成到CMOS器件的源极或漏极的触点。 表面张力降低层设置在PMOS晶体管的源极或漏极区域和上覆表面张力诱导层之间。 表面张力诱导层可以包括氮化物材料或含碳材料，并且表面张力减小层可以包括氧化物材料。 通过使用双层蚀刻停止层的表面张力降低层来防止PMOS晶体管中空穴迁移率的降低。

公开(公告)号：US07190033B2

公开(公告)日：2007-03-13

申请号：US10826956

申请日：2004-04-15

申请人： Sun-Jay Chang ,  Chien-Li Cheng

发明人： Sun-Jay Chang ,  Chien-Li Cheng

IPC分类号： H01L29/76

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/7843

摘要： A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer is disposed between the source or drain region of the PMOS transistor and an overlying surface tension-inducing layer. The surface tension-inducing layer may comprise a nitride material or carbon-containing material, and the surface tension-reducing layer may comprise an oxide material. Degradation of hole mobility in the PMOS transistor is prevented by the use of the surface tension-reducing layer of the bilayer etch stop.

摘要翻译： 一种CMOS器件及其制造方法，其中在PMOS晶体管上使用双层蚀刻停止，并且单个蚀刻停止层用于NMOS晶体管，用于形成到CMOS器件的源极或漏极的触点。 表面张力降低层设置在PMOS晶体管的源极或漏极区域和上覆表面张力诱导层之间。 表面张力诱导层可以包括氮化物材料或含碳材料，并且表面张力减小层可以包括氧化物材料。 通过使用双层蚀刻停止层的表面张力降低层来防止PMOS晶体管中空穴迁移率的降低。

公开(公告)号：US20130270620A1

公开(公告)日：2013-10-17

申请号：US13444623

申请日：2012-04-11

申请人： Chia-Hsin Hu ,  Sun-Jay Chang

发明人： Chia-Hsin Hu ,  Sun-Jay Chang

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/0629 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L28/40 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure provides one embodiment of a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T1 and a second portion disposed in the second region and having a second thickness T2 greater than the first depth, the first portion of the STI feature being recessed from the second portion of the STI feature. The semiconductor structure also includes a plurality of fin active regions on the semiconductor substrate; and a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region.

摘要翻译： 本公开提供了半导体结构的一个实施例，其包括具有第一区域和第二区域的半导体衬底; 形成在半导体衬底中的浅沟槽隔离（STI）特征。 STI特征包括设置在第一区域中并且具有第一厚度T1和设置在第二区域中的第二部分并且具有大于第一深度的第二厚度T2的第一部分，STI特征的第一部分从 STI特征的第二部分。 半导体结构还包括在半导体衬底上的多个翅片有源区; 以及设置在翅片有源区域和STI特征上的多个导电特征，其中导电特征之一覆盖第一区域中的STI特征的第一部分。

公开(公告)号：US20130200455A1

公开(公告)日：2013-08-08

申请号：US13369116

申请日：2012-02-08

申请人： Wen-Cheng Lo ,  Sun-Jay Chang

发明人： Wen-Cheng Lo ,  Sun-Jay Chang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/265 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

摘要： A method for performing a stress memorization technique (SMT) a FinFET and a FinFET having memorized stress effects including multi-planar dislocations are disclosed. An exemplary embodiment includes receiving a FinFET precursor with a substrate, a fin structure on the substrate, an isolation region between the fin structures, and a gate stack over a portion of the fin structure. The gate stack separates a source region of the fin structure from a drain region of the fin structure and creates a gate region between the two. The embodiment also includes forming a stress-memorization technique (SMT) capping layer over at least a portion of each of the fin structures, isolation regions, and the gate stack, performing a pre-amorphization implant on the FinFET precursor by implanting an energetic doping species, performing an annealing process on the FinFET precursor, and removing the SMT capping layer.

摘要翻译： 公开了一种用于执行应力记忆技术（SMT）的FinFET和具有包括多平面位错的记忆应力作用的FinFET的方法。 示例性实施例包括接收具有衬底的FinFET前体，衬底上的翅片结构，鳍结构之间的隔离区域和翅片结构的一部分上的栅极堆叠。 栅极堆叠将鳍状结构的源极区域与鳍状结构的漏极区分离，并在两者之间形成栅极区域。 该实施例还包括在每个翅片结构，隔离区域和栅极堆叠的至少一部分上形成应力记忆技术（SMT）覆盖层，通过注入能量掺杂来对FinFET前体进行预非晶化注入 对FinFET前体进行退火处理，并移除SMT封盖层。

公开(公告)号：US20050260810A1

公开(公告)日：2005-11-24

申请号：US10851377

申请日：2004-05-21

申请人： Kaun-Lun Cheng ,  Shui-Ming Cheng ,  Yu-Yuan Yao ,  Ka-Hing Fung ,  Sun-Jay Chang

发明人： Kaun-Lun Cheng ,  Shui-Ming Cheng ,  Yu-Yuan Yao ,  Ka-Hing Fung ,  Sun-Jay Chang

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828

摘要： A strained channel MOSFET device with improved charge carrier mobility and method for forming the same, the method including providing a first and second FET device having a respective first polarity and second polarity opposite the first polarity on a substrate; forming a strained layer having a stress selected from the group consisting of compressive and tensile on the first and second FET devices; and, removing a thickness portion of the strained layer over one of the first and second FET devices to improve charge carrier mobility.

摘要翻译： 一种具有改善的电荷载流子迁移率的应变沟道MOSFET器件及其形成方法，所述方法包括：在衬底上提供具有与第一极性相反的第一极性和第二极性的第一和第二FET器件; 形成在第一和第二FET器件上具有选自压缩和拉伸的应力的应变层; 并且通过所述第一和第二FET器件中的一个去除所述应变层的厚度部分以改善电荷载流子迁移率。

公开(公告)号：US06885214B1

公开(公告)日：2005-04-26

申请号：US10689431

申请日：2003-10-20

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Kuan-Yao Wang ,  Sun-Jay Chang

IPC分类号： G01R31/26

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G01R31/2644

摘要： An apparatus for characterizing capacitance and thickness of an insulating layer constructed between a conductive gate and a substrate has at least one test structure formed at a surface of a substrate. Each test structure has a bulk region formed of a semiconductor within the surface. Further the test structure has at least one source region and one drain region within the bulk region. A thin insulating layer is placed above the each source region, each drain region, and the bulk region. A conductive gate is placed above the thin insulating layer. A capacitance-voltage measuring device measures a capacitance value of the test structure, while forcing the bulk region between the source region and the drain region to be floating. An insulating layer thickness calculator determines the thickness of the insulating layer from the capacitance.

摘要翻译： 用于表征在导电栅极和衬底之间构造的绝缘层的电容和厚度的装置具有形成在衬底表面上的至少一个测试结构。 每个测试结构具有由表面内的半导体形成的体区。 此外，测试结构在体区内具有至少一个源极区和一个漏极区。 在每个源极区域，每个漏极区域和主体区域上方放置薄的绝缘层。 导电栅极位于薄绝缘层的上方。 电容电压测量装置测量测试结构的电容值，同时迫使源极区域和漏极区域之间的体区域浮动。 绝缘层厚度计算器根据电容确定绝缘层的厚度。

公开(公告)号：US20070290277A1

公开(公告)日：2007-12-20

申请号：US11844161

申请日：2007-08-23

申请人： Sun-Jay Chang ,  Shien-Yang Wu

发明人： Sun-Jay Chang ,  Shien-Yang Wu

IPC分类号： H01L29/94

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7849

摘要： A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily-doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.

摘要翻译： 提供一种用于制造具有由硅 - 锗组分构成的沟道区的MOSFET器件的工艺。 工艺特征采用成角度的离子注入方法，将锗离子放置在导电栅极结构下面的半导体衬底的区域中。 用作随后的高掺杂源极/漏极区域的扩散源的凸起硅形状的存在，导电栅极结构的存在以及先前位于导电栅极结构上的虚设绝缘体的去除允许成角度的注入过程放置 在半导体衬底的用于MOSFET沟道区域的部分中的锗离子。 退火程序导致在用于MOSFET沟道区的半导体衬底的部分中形成所需的硅 - 锗组分。

公开(公告)号：US07279430B2

公开(公告)日：2007-10-09

申请号：US10919684

申请日：2004-08-17

申请人： Sun-Jay Chang ,  Shien-Yang Wu

发明人： Sun-Jay Chang ,  Shien-Yang Wu

IPC分类号： H01L21/302

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7849

摘要： A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.

摘要翻译： 提供一种用于制造具有由硅 - 锗组分构成的沟道区的MOSFET器件的工艺。 工艺特征采用成角度的离子注入方法，将锗离子放置在导电栅极结构下面的半导体衬底的区域中。 用作随后的重掺杂源极/漏极区域的扩散源的凸起硅形状的存在，导电栅极结构的存在以及先前位于导电栅极结构上的虚设绝缘体的去除允许成角度的注入过程将锗 半导体衬底的一部分中用于MOSFET沟道区的离子。 退火程序导致在用于MOSFET沟道区的半导体衬底的部分中形成所需的硅 - 锗组分。