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公开(公告)号：US07958383B2
公开(公告)日：2011-06-07
申请号：US12191411
申请日：2008-08-14
申请人： Chien-Ping Chung , Cheng-Wei Huang , Chi Chang
发明人： Chien-Ping Chung , Cheng-Wei Huang , Chi Chang
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/126 , Y02D10/151
摘要： A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power management control signal issued by the core logic chip. For adjusting data transmission rate between the CPU and the core logic chip, a change of an asserted time of the power management control signal from a first time period to a second time period is first determined to obtain an index value. The data transmission rate is increased or decreased according to the index value.
摘要翻译： 计算机系统具有在CPU和其核心逻辑芯片之间的可调数据传输速率。 在计算机系统中，CPU具有响应于由核心逻辑芯片发出的功率管理控制信号而调整的功率状态。 为了调整CPU和核心逻辑芯片之间的数据传输速率，首先确定功率管理控制信号从第一时间段到第二时间段的断言时间的改变以获得索引值。 数据传输速率根据指标值增减。
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公开(公告)号：US20090049327A1
公开(公告)日：2009-02-19
申请号：US12191411
申请日：2008-08-14
申请人： Chien-Ping Chung , Cheng-Wei Huang , Chi Chang
发明人： Chien-Ping Chung , Cheng-Wei Huang , Chi Chang
IPC分类号： G06F5/06
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/126 , Y02D10/151
摘要： A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power management control signal issued by the core logic chip. For adjusting data transmission rate between the CPU and the core logic chip, a change of an asserted time of the power management control signal from a first time period to a second time period is first determined to obtain an index value. The data transmission rate is increased or decreased according to the index value.
摘要翻译： 计算机系统具有在CPU和其核心逻辑芯片之间的可调数据传输速率。 在计算机系统中，CPU具有响应于由核心逻辑芯片发出的功率管理控制信号而调整的功率状态。 为了调整CPU和核心逻辑芯片之间的数据传输速率，首先确定功率管理控制信号从第一时间段到第二时间段的断言时间的改变以获得索引值。 数据传输速率根据指标值增减。
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公开(公告)号：US20080222409A1
公开(公告)日：2008-09-11
申请号：US12000591
申请日：2007-12-14
申请人： Chien-Ping Chung , Lin-Hung Chen
发明人： Chien-Ping Chung , Lin-Hung Chen
IPC分类号： G06F12/02 , G06F15/177
CPC分类号： G06F12/0223 , G06F9/4403 , G06F12/0284 , G06F2212/2022
摘要： A memory access system for accessing a basic input output system (BIOS) program is provided. The memory access system includes a flash memory, a CPU, a peripheral component interconnect (PCI) slave, an address converter and a flash memory controller. The flash memory stores a number of BIOS data of the BIOS program, and each BIOS data corresponds to a default BIOS address and is allocated in a flash memory type BIOS address. The CPU delivers a BIOS access instruction. The BIOS access instruction corresponds to a default target address of the default BIOS addresses. After the PCI slave interprets the BIOS access instruction, the address converter converts the default target address into a flash memory type target address, which is one of the flash memory type BIOS address. The flash memory controller accesses the BIOS data allocated at the flash memory type target address accordingly.
摘要翻译： 提供了用于访问基本输入输出系统（BIOS）程序的存储器访问系统。 存储器访问系统包括闪存，CPU，外围组件互连（PCI）从站，地址转换器和闪存控制器。 闪存存储BIOS程序的多个BIOS数据，并且每个BIOS数据对应于默认BIOS地址，并且被分配在闪速存储器类型的BIOS地址中。 CPU提供BIOS访问指令。 BIOS访问指令对应于默认的BIOS地址的默认目标地址。 在PCI从站解读BIOS访问指令后，地址转换器将默认目标地址转换为Flash存储器类型的BIOS地址之一的闪存类型目标地址。 闪存控制器相应地访问在闪存类型目标地址处分配的BIOS数据。
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公开(公告)号：US20080222345A1
公开(公告)日：2008-09-11
申请号：US11945311
申请日：2007-11-27
IPC分类号： G06F12/00
CPC分类号： G06F12/1416 , G06F9/30003 , G06F2212/2022
摘要： A memory access method for accessing data from a non-volatile memory in a south bridge is provided. Memory access is performed under a system management mode (SMM). Under the protection of the SMM mode, the desired memory address is not altered by an interrupt handler, therefore memory data is accessed correctly.
摘要翻译： 提供了一种用于从南桥的非易失性存储器访问数据的存储器访问方法。 在系统管理模式（SMM）下执行内存访问。 在SMM模式的保护下，所需的存储器地址不会被中断处理程序改变，因此存储器数据被正确访问。
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公开(公告)号：US20050204088A1
公开(公告)日：2005-09-15
申请号：US11051449
申请日：2005-02-04
申请人： Kuan-Jui Ho , Stephen Chen , Ruei-Ling Lin , Chien-Ping Chung
发明人： Kuan-Jui Ho , Stephen Chen , Ruei-Ling Lin , Chien-Ping Chung
CPC分类号： G06F13/28
摘要： Data acquisition methods and systems in support of non-snoop transactions. In the data acquisition method, the cache memory is partially written back and invalidate, such that a portion of the data in the cache memory is written back to the DMA buffer. The endpoint device is directed to use a non-snoop transaction to read the data stored in the DMA buffer. The data stored in the DMA buffer is acquired directly without snooping the processor when receiving a non-snoop read transaction.
摘要翻译： 数据采集方法和系统支持非侦听事务。 在数据采集方法中，高速缓冲存储器部分地被写回并使其无效，使得高速缓冲存储器中的一部分数据被写回到DMA缓冲器。 端点设备被指示使用非窥探事务来读取存储在DMA缓冲器中的数据。 存储在DMA缓冲器中的数据直接获取，而不会在接收到非窥探读取事务时窥探处理器。
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公开(公告)号：US07991990B2
公开(公告)日：2011-08-02
申请号：US12000591
申请日：2007-12-14
申请人： Chien-Ping Chung , Lin-Hung Chen
发明人： Chien-Ping Chung , Lin-Hung Chen
CPC分类号： G06F12/0223 , G06F9/4403 , G06F12/0284 , G06F2212/2022
摘要： A memory access system for accessing a basic input output system (BIOS) program is provided. The memory access system includes a flash memory, a CPU, a peripheral component interconnect (PCI) slave, an address converter and a flash memory controller. The flash memory stores a number of BIOS data of the BIOS program, and each BIOS data corresponds to a default BIOS address and is allocated in a flash memory type BIOS address. The CPU delivers a BIOS access instruction. The BIOS access instruction corresponds to a default target address of the default BIOS addresses. After the PCI slave interprets the BIOS access instruction, the address converter converts the default target address into a flash memory type target address, which is one of the flash memory type BIOS address. The flash memory controller accesses the BIOS data allocated at the flash memory type target address accordingly.
摘要翻译： 提供了用于访问基本输入输出系统（BIOS）程序的存储器访问系统。 存储器访问系统包括闪存，CPU，外围组件互连（PCI）从站，地址转换器和闪存控制器。 闪存存储BIOS程序的多个BIOS数据，并且每个BIOS数据对应于默认BIOS地址，并且被分配在闪速存储器类型的BIOS地址中。 CPU提供BIOS访问指令。 BIOS访问指令对应于默认的BIOS地址的默认目标地址。 在PCI从站解读BIOS访问指令后，地址转换器将默认目标地址转换为Flash存储器类型的BIOS地址之一的闪存类型目标地址。 闪存控制器相应地访问在闪存类型目标地址处分配的BIOS数据。
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公开(公告)号：US07861044B2
公开(公告)日：2010-12-28
申请号：US11945311
申请日：2007-11-27
CPC分类号： G06F12/1416 , G06F9/30003 , G06F2212/2022
摘要： A memory access method for accessing data from a non-volatile memory in a south bridge is provided. Memory access is performed under a system management mode (SMM). Under the protection of the SMM mode, the desired memory address is not altered by an interrupt handler, therefore memory data is accessed correctly.
摘要翻译： 提供了一种用于从南桥的非易失性存储器访问数据的存储器访问方法。 在系统管理模式（SMM）下执行内存访问。 在SMM模式的保护下，所需的存储器地址不会被中断处理程序改变，因此存储器数据被正确访问。
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公开(公告)号：US20080012585A1
公开(公告)日：2008-01-17
申请号：US11622027
申请日：2007-01-11
IPC分类号： G01R27/08
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Apparatus and methods of adjusting system efficiency for a current-consuming system are disclosed. In the disclosed apparatus, a system current detector receives a system current from the current-consuming system and calculates a system current variation accordingly. A system efficiency adjustment module is coupled to the system current detector to receive the system current variation and output a frequency control signal and a voltage control signal accordingly.
摘要翻译： 公开了一种调节耗电系统效率的装置和方法。 在所公开的装置中，系统电流检测器从耗电系统接收系统电流并相应地计算系统电流变化。 系统效率调节模块耦合到系统电流检测器以接收系统电流变化并相应地输出频率控制信号和电压控制信号。
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公开(公告)号：US20060031690A1
公开(公告)日：2006-02-09
申请号：US10963149
申请日：2004-10-12
IPC分类号： G06F1/30
CPC分类号： G06F1/324 , G06F1/3203 , Y02D10/126
摘要： A system and method for power management in computer systems. System status assessed by a Northbridge, and the result transferred to a Southbridge. A system control table is provided in the Southbridge, whereby power management without software control is provided.
摘要翻译： 计算机系统中电源管理的系统和方法。 由北桥评估的系统状态，结果转移到南桥。 在南桥提供了一个系统控制表，从而提供无需软件控制的电源管理。
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公开(公告)号：US20100169555A1
公开(公告)日：2010-07-01
申请号：US12632668
申请日：2009-12-07
申请人： Chien-Ping Chung , Chia-Hsin Chen , Ming-Che Liu
发明人： Chien-Ping Chung , Chia-Hsin Chen , Ming-Che Liu
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7206
摘要： A method of writing data into flash memory based on OS file system is provided. The method includes steps of: obtaining a data start position of a data area in a first partition of a flash memory; converting the data start position into a first block number and a first page number; calculating an offset and adding the offset to the first page number to be an updated first page number when the first page number is not an integer; and, setting the first block number and the updated first page number as a new data start position of the data area and writing a first data according to the new data start position.
摘要翻译： 提供了一种基于OS文件系统将数据写入闪存的方法。 该方法包括以下步骤：获取快闪存储器的第一分区中的数据区的数据开始位置; 将数据开始位置转换成第一块号和第一页号; 当第一页数不是整数时，计算偏移量并将偏移量添加到第一页数作为更新的第一页数; 并且将第一块号和更新的第一页号设置为数据区的新数据开始位置，并根据新数据开始位置写入第一数据。
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