公开(公告)号：US06191019B1

公开(公告)日：2001-02-20

申请号：US09229231

申请日：1999-01-12

申请人： Chih-Cherng Liao ,  Jiunn-Liang Yu ,  Chan-Jen Kuo ,  Chi-San Wu ,  Yun-Chi Jiang

发明人： Chih-Cherng Liao ,  Jiunn-Liang Yu ,  Chan-Jen Kuo ,  Chi-San Wu ,  Yun-Chi Jiang

IPC分类号： H01L213205

CPC分类号： H01L21/28061

摘要： A method for preventing void formation in a gate of a transistor formed in a substrate is disclosed. The method comprises: forming a gate oxide layer on the substrate; forming a polysilicon layer on the gate oxide layer; performing an ion implantation on the polysilicon layer, the ion implantation performed with a power approximately 30 KeV and a dosage about more than 1015 atoms/cm2; and forming a silicide layer on the polysilicon layer.

摘要翻译： 公开了一种用于防止形成在衬底中的晶体管的栅极中形成空穴的方法。 该方法包括：在衬底上形成栅氧化层; 在栅氧化层上形成多晶硅层; 在多晶硅层上进行离子注入，以大约30keV的功率和大于1015个原子/ cm2的剂量进行离子注入; 以及在所述多晶硅层上形成硅化物层。

公开(公告)号：US6057218A

公开(公告)日：2000-05-02

申请号：US307404

申请日：1999-05-07

申请人： Jiunn-Liang Yu ,  Chih-Cherng Liao ,  Chen-Jen Kuo

发明人： Jiunn-Liang Yu ,  Chih-Cherng Liao ,  Chen-Jen Kuo

IPC分类号： H01L21/8234 ,  H01L21/28

CPC分类号： H01L21/82345

摘要： The present invention discloses a method for simultaneously manufacturing a poly gate and a polycide gate which requires only one gate oxide layer deposition and one polysilicon layer deposition steps by incorporating a protective layer, primarily an oxide layer, which acts as a mask of a silicide. The present invention not only simplifies the process but also avoids a residual spacer in the gate. The advantages also includes widening the process window, controlling the gate channel and avoiding the gate top loss.

摘要翻译： 本发明公开了一种用于同时制造多晶硅栅极和多晶硅栅极的方法，其仅需要一个栅极氧化物层沉积和一个多晶硅层沉积步骤，其中通过引入作为硅化物掩模的保护层，主要是氧化物层。 本发明不仅简化了工艺过程，而且避免了栅极中的残余间隔物。 优点还包括扩大工艺窗口，控制栅极通道并避免栅极顶部损耗。

公开(公告)号：US20060027890A1

公开(公告)日：2006-02-09

申请号：US11246092

申请日：2005-10-11

申请人： Jia-Wei Yang ,  Chih-Cherng Liao

发明人： Jia-Wei Yang ,  Chih-Cherng Liao

IPC分类号： H01L29/00

CPC分类号： H01L21/763

摘要： A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial layer. An ion diffusion region with the first type conductivity is formed in the epitaxial layer and surrounds the sidewall and bottom of the deep trench. An undoped polysilicon layer fills the deep trench.

摘要翻译： 高压器件的深沟槽隔离结构及其形成方法。 在具有第一类型导电性的半导体硅衬底上形成具有第二类型导电性的外延层。 深沟槽穿过外延层。 在外延层中形成具有第一类型导电性的离子扩散区，并且围绕深沟槽的侧壁和底部。 未掺杂的多晶硅层填充深沟槽。

公开(公告)号：US06713338B2

公开(公告)日：2004-03-30

申请号：US10315992

申请日：2002-12-11

申请人： Wen-Tsung Wang ,  Yi-Tsung Jan ,  Sung-Min Wei ,  Chih-Cherng Liao ,  Zhe-Xiong Wu ,  Mao-Tsung Chen ,  Yuan-Heng Li

发明人： Wen-Tsung Wang ,  Yi-Tsung Jan ,  Sung-Min Wei ,  Chih-Cherng Liao ,  Zhe-Xiong Wu ,  Mao-Tsung Chen ,  Yuan-Heng Li

IPC分类号： H01L218238

CPC分类号： H01L29/66659 ,  H01L29/7835

摘要： A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed thereon, a first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate less than half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.

摘要翻译： 一种用于制造源极/漏极器件的方法。 半导体衬底上形成有栅极，在半导体衬底上的栅极的第一侧上形成第一掺杂区域，并且以半导体衬底上的栅极的第二侧上形成第二掺杂区域 使得第二掺杂区域与栅极分离预定距离。 在半导体衬底上形成图案化的光致抗蚀剂层，该半导体衬底在第二侧具有开口，暴露的栅极小于栅极宽度的一半。 使用图案化的光致抗蚀剂层作为掩模，将半导体衬底注入和退火以在栅极的第二侧上形成双重扩散区域。

公开(公告)号：US06972471B2

公开(公告)日：2005-12-06

申请号：US10354130

申请日：2003-01-30

申请人： Jia-Wei Yang ,  Chih-Cherng Liao

发明人： Jia-Wei Yang ,  Chih-Cherng Liao

IPC分类号： H01L21/763 ,  H01L29/00 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L21/763

摘要： A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial layer. An ion diffusion region with the first type conductivity is formed in the epitaxial layer and surrounds the sidewall and bottom of the deep trench. An undoped polysilicon layer fills the deep trench.

摘要翻译： 高压器件的深沟槽隔离结构及其形成方法。 在具有第一类型导电性的半导体硅衬底上形成具有第二类型导电性的外延层。 深沟槽穿过外延层。 在外延层中形成具有第一类型导电性的离子扩散区，并且围绕深沟槽的侧壁和底部。 未掺杂的多晶硅层填充深沟槽。

公开(公告)号：US06680231B1

公开(公告)日：2004-01-20

申请号：US10301686

申请日：2002-11-22

申请人： Jia-Wei Yang ,  Chih-Cherng Liao

发明人： Jia-Wei Yang ,  Chih-Cherng Liao

IPC分类号： H01L21336

CPC分类号： H01L21/823493 ,  H01L21/823462 ,  H01L27/088

摘要： A high-voltage device process compatible with a low-voltage device process. A high-voltage device area and a low-voltage device area are defined on an epitaxial layer of a semiconductor substrate. After forming a plurality of first gate structures on the high-voltage device area, a P-body is formed in the epitaxial layer between two adjacent first gate structures. Then, a plurality of second gate structures is formed on the low-voltage device area.

摘要翻译： 兼容低压器件工艺的高压器件工艺。 在半导体衬底的外延层上限定高压器件区域和低电压器件区域。 在高压器件区域上形成多个第一栅极结构之后，在两个相邻的第一栅极结构之间的外延层中形成P体。 然后，在低电压装置区域上形成多个第二栅极结构。

公开(公告)号：US5583070A

公开(公告)日：1996-12-10

申请号：US499744

申请日：1995-07-07

申请人： Chih-Cherng Liao ,  Haw Yen

发明人： Chih-Cherng Liao ,  Haw Yen

IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/265

CPC分类号： H01L27/10852 ,  H01L21/3213 ,  H01L28/84 ,  Y10S148/014 ,  Y10S438/954 ,  Y10S438/964

摘要： A process for fabricating stacked capacitor, DRAM, devices, has been developed in which the surface area of the storage node has been significantly increased as a result of a unique set of deposition and annealing conditions. An amorphous polysilicon layer, used as the upper layer of the storage node, is ramped up in pure nitrogen, and then insitu annealed, to result in a polycrystalline structure, exhibiting significant surface area increases, due to the formation of surface concave and convex protrusions. The increase in storage node surface area allows for increased DRAM capacitance, without the use of larger dimension stacked capacitors, or thinner dielectrics.

摘要翻译： 已经开发了用于制造堆叠电容器，DRAM，器件的方法，其中由于独特的沉积和退火条件，存储节点的表面积已经显着增加。 用作存储节点的上层的非晶多晶硅层在纯氮中上升，然后进行自组织退火，从而导致多晶结构，由于形成表面凹凸突起而表现出显着的表面积增加 。 存储节点表面积的增加允许增加DRAM电容，而不使用较大尺寸的堆叠电容器或更薄的电介质。

公开(公告)号：US20060220117A1

公开(公告)日：2006-10-05

申请号：US11441246

申请日：2006-05-26

申请人： Jia-Wei Yang ,  Da-Pong Chang ,  Chih-Cherng Liao

发明人： Jia-Wei Yang ,  Da-Pong Chang ,  Chih-Cherng Liao

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/7801

摘要： A structure for an LDMOS transistor has a horseshoe-shaped gate layer formed on an N-type layer of a semiconductor silicon substrate, in which the gate layer comprises a transverse-extending area, a first lengthwise-extending area connected to a left end of the transverse-extending area and a second lengthwise-extending area connected to a right end of the transverse-extending area. A first P-type body is formed in the N-type layer, and overlaps the left periphery of the first lengthwise-extending area of the gate layer. A second P-type body is formed in the N-type layer, and overlaps the right periphery of the second lengthwise-extending area of the gate layer.

公开(公告)号：US07041572B2

公开(公告)日：2006-05-09

申请号：US10793773

申请日：2004-03-08

申请人： Jia-Wei Yang ,  Chih-Cherng Liao

发明人： Jia-Wei Yang ,  Chih-Cherng Liao

IPC分类号： H01L21/76 ,  H01L21/336

CPC分类号： H01L21/763

摘要： A fabrication method for a semiconductor device. On a semiconductor silicon substrate with a first type conductivity, an epitaxial layer with a second type conductivity and an oxide layer on the epitaxial layer are formed with at least a deep trench. Ion implantation is used to form an ion diffusion region with the first type conductivity which is formed in the epitaxial layer and surrounds the sidewall and bottom of the deep trench. An oxide liner is formed on the sidewall and bottom of the deep trench, and then an undoped polysilicon layer is formed to fill the deep trench. The combination of the ion diffusion region and the undoped polysilicon layer serves as a deep trench isolation structure.

摘要翻译： 一种半导体器件的制造方法。 在具有第一类型导电性的半导体硅衬底上，至少形成深沟槽，在外延层上形成具有第二导电性的外延层和氧化物层。 离子注入用于形成具有第一类型导电性的离子扩散区，其形成在外延层中并且围绕深沟槽的侧壁和底部。 在深沟槽的侧壁和底部形成氧化物衬垫，然后形成未掺杂的多晶硅层以填充深沟槽。 离子扩散区域和未掺杂的多晶硅层的组合用作深沟槽隔离结构。

公开(公告)号：US06835636B2

公开(公告)日：2004-12-28

申请号：US10315980

申请日：2002-12-11

申请人： Yi-Tsung Jan ,  Wen-Tsung Wang ,  Sung-Min Wei ,  Chih-Cherng Liao ,  Zhe-Xiong Wu ,  Mao-Tsang Chen ,  Yuan-Heng Li

发明人： Yi-Tsung Jan ,  Wen-Tsung Wang ,  Sung-Min Wei ,  Chih-Cherng Liao ,  Zhe-Xiong Wu ,  Mao-Tsang Chen ,  Yuan-Heng Li

IPC分类号： H01L213205

CPC分类号： H01L29/66659 ,  H01L29/7835

摘要： A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed on the semiconductor substrate, and a hard mask layer formed on the gate. A first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate equal to half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer and the hard mask layer as masks.

摘要翻译： 一种用于制造源极/漏极器件的方法。 在半导体衬底上设置有形成在半导体衬底上的栅极和形成在栅极上的硬掩模层。 第一掺杂区域形成在半导体衬底上的栅极的第一侧上，并且第二掺杂区域以这样的方式形成在半导体衬底上的栅极的第二侧上，使得第二掺杂区域与栅极分离 预定距离。 在具有在第二侧上具有开口的半导体衬底上形成图案化的光致抗蚀剂层，暴露的栅极等于栅极宽度的一半。 使用图案化的光致抗蚀剂层和硬掩模层作为掩模，将半导体衬底注入和退火以在栅极的第二侧上形成双重扩散区域。