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    Image sensor having compressive layers
    3.
    发明授权
    Image sensor having compressive layers 有权
    具有压缩层的图像传感器

    公开(公告)号：US09059057B2

    公开(公告)日：2015-06-16

    申请号：US13492258

    申请日：2012-06-08

    申请人： Chun-Han Tsao ,  Chih-Yu Lai ,  Chih-Hui Huang ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Ching-Chun Wang ,  Shyh-Fann Ting ,  Chia-Shiung Tsai

    发明人： Chun-Han Tsao ,  Chih-Yu Lai ,  Chih-Hui Huang ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Ching-Chun Wang ,  Shyh-Fann Ting ,  Chia-Shiung Tsai

    IPC分类号： H01L31/102 ,  H01L21/00 ,  H01L27/146 ,  H01L27/148

    CPC分类号： H01L31/02164 ,  H01L27/14623 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/148 ,  H01L51/4273

    摘要： An image sensor device including a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon oxide, and is negatively charged. The second compressively-stressed layer contains silicon nitride, and is negatively charged. A metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a third compressively-stressed layer formed on the metal shield and the second compressively-stressed layer. The third compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the third compressively-stressed layer.

    摘要翻译： 一种包括具有阵列区域和黑色电平校正区域的半导体衬底的图像传感器装置。 阵列区域包含多个辐射敏感像素。 黑色电平校正区域包含一个或多个参考像素。 基板具有前侧和后侧。 图像传感器装置包括形成在基板的背面上的第一压缩应力层。 第一压应力层含有氧化硅，带负电荷。 第二压应力层含有氮化硅，带负电荷。 在黑色电平校正区域的至少一部分上形成金属屏蔽。 图像传感器装置包括形成在金属屏蔽和第二压缩应力层上的第三压缩应力层。 第三压缩应力层含有氧化硅。 金属屏蔽层的侧壁由第三压应力层保护。

    Backside Surface Treatment of Semiconductor Chips
    5.
    发明申请
    Backside Surface Treatment of Semiconductor Chips 有权
    半导体芯片的背面表面处理

    公开(公告)号：US20130040446A1

    公开(公告)日：2013-02-14

    申请号：US13205179

    申请日：2011-08-08

    申请人： Chih-Yu Lai ,  Cheng-Ta Wu ,  Kai-Chun Hsu ,  Yeur-Luen Tu ,  Ching-Chun Wang ,  Chia-Shiung Tsai

    发明人： Chih-Yu Lai ,  Cheng-Ta Wu ,  Kai-Chun Hsu ,  Yeur-Luen Tu ,  Ching-Chun Wang ,  Chia-Shiung Tsai

    IPC分类号： H01L21/265

    CPC分类号： H01L27/14687 ,  H01L27/1464

    摘要： A method includes performing a grinding to a backside of a semiconductor substrate, wherein a remaining portion of the semiconductor substrate has a back surface. A treatment is then performed on the back surface using a method selected from the group consisting essentially of a dry treatment and a plasma treatment. Process gases that are used in the treatment include oxygen (O2). The plasma treatment is performed without vertical bias in a direction perpendicular to the back surface.

    摘要翻译： 一种方法包括对半导体衬底的背面进行研磨，其中半导体衬底的剩余部分具有背面。 然后使用基本上由干法处理和等离子体处理组成的组中的方法在背面进行处理。 用于处理的工艺气体包括氧（O 2）。 在垂直于后表面的方向上进行等离子体处理而没有垂直偏压。

    Method of reducing delamination in the fabrication of small-pitch devices
    6.
    发明授权
    Method of reducing delamination in the fabrication of small-pitch devices 有权
    减少小间距装置制造中分层的方法

    公开(公告)号：US08778807B2

    公开(公告)日：2014-07-15

    申请号：US13253694

    申请日：2011-10-05

    申请人： Chih-Yu Lai ,  Cheng-Ta Wu ,  Neng-Kuo Chen ,  Cheng-Yuan Tsai

    发明人： Chih-Yu Lai ,  Cheng-Ta Wu ,  Neng-Kuo Chen ,  Cheng-Yuan Tsai

    IPC分类号： H01L21/302

    CPC分类号： H01L21/0337

    摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.

    摘要翻译： 形成集成电路结构的方法包括提供基板; 在衬底上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层; 图案化第二硬掩模层以形成硬掩模; 并且在图案化第二硬掩模层的步骤之后，烘烤基板，第一硬掩模层和硬掩模。 在烘烤步骤之后，形成间隔层，其包括在硬掩模的顶部上的第一部分和硬掩模的相对侧壁上的第二部分和第三部分。 该方法还包括去除间隔层的第一部分; 去除硬面膜; 并且使用间隔层的第二部分和第三部分作为掩模来对第一硬掩模层进行图案化。

    Method of Reducing Delamination in the Fabrication of Small-Pitch Devices
    7.
    发明申请
    Method of Reducing Delamination in the Fabrication of Small-Pitch Devices 有权
    减小小间距器件制造中分层的方法

    公开(公告)号：US20100136791A1

    公开(公告)日：2010-06-03

    申请号：US12326099

    申请日：2008-12-01

    申请人： Chih-Yu Lai ,  Cheng-Ta Wu ,  Neng-Kuo Chen ,  Cheng-Yuan Tsai

    发明人： Chih-Yu Lai ,  Cheng-Ta Wu ,  Neng-Kuo Chen ,  Cheng-Yuan Tsai

    IPC分类号： H01L21/308 ,  H01L21/30

    CPC分类号： H01L21/0337

    摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.

    摘要翻译： 形成集成电路结构的方法包括提供基板; 在衬底上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层; 图案化第二硬掩模层以形成硬掩模; 并且在图案化第二硬掩模层的步骤之后，烘烤基板，第一硬掩模层和硬掩模。 在烘烤步骤之后，形成间隔层，其包括在硬掩模的顶部上的第一部分和硬掩模的相对侧壁上的第二部分和第三部分。 该方法还包括去除间隔层的第一部分; 去除硬面膜; 并且使用间隔层的第二部分和第三部分作为掩模来对第一硬掩模层进行图案化。

    Method of reducing delamination in the fabrication of small-pitch devices
    8.
    发明授权
    Method of reducing delamination in the fabrication of small-pitch devices 有权
    减少小间距装置制造中分层的方法

    公开(公告)号：US08048813B2

    公开(公告)日：2011-11-01

    申请号：US12326099

    申请日：2008-12-01

    申请人： Chih-Yu Lai ,  Cheng-Ta Wu ,  Neng-Kuo Chen ,  Cheng-Yuan Tsai

    发明人： Chih-Yu Lai ,  Cheng-Ta Wu ,  Neng-Kuo Chen ,  Cheng-Yuan Tsai

    IPC分类号： H01L21/302

    CPC分类号： H01L21/0337

    摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.

    摘要翻译： 形成集成电路结构的方法包括提供基板; 在衬底上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层; 图案化第二硬掩模层以形成硬掩模; 并且在图案化第二硬掩模层的步骤之后，烘烤基板，第一硬掩模层和硬掩模。 在烘烤步骤之后，形成间隔层，其包括在硬掩模的顶部上的第一部分和硬掩模的相对侧壁上的第二部分和第三部分。 该方法还包括去除间隔层的第一部分; 去除硬面膜; 并且使用间隔层的第二部分和第三部分作为掩模来对第一硬掩模层进行图案化。

    Method of Reducing Delamination in the Fabrication of Small-Pitch Devices
    9.
    发明申请
    Method of Reducing Delamination in the Fabrication of Small-Pitch Devices 有权
    减小小间距器件制造中分层的方法

    公开(公告)号：US20120028473A1

    公开(公告)日：2012-02-02

    申请号：US13253694

    申请日：2011-10-05

    申请人： Chih-Yu Lai ,  Cheng-Ta Wu ,  Neng-Kuo Chen ,  Cheng-Yuan Tsai

    发明人： Chih-Yu Lai ,  Cheng-Ta Wu ,  Neng-Kuo Chen ,  Cheng-Yuan Tsai

    IPC分类号： H01L21/302

    CPC分类号： H01L21/0337

    摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.

    摘要翻译： 形成集成电路结构的方法包括提供基板; 在衬底上形成第一硬掩模层; 在所述第一硬掩模层上形成第二硬掩模层; 图案化第二硬掩模层以形成硬掩模; 并且在图案化第二硬掩模层的步骤之后，烘烤基板，第一硬掩模层和硬掩模。 在烘烤步骤之后，形成间隔层，其包括在硬掩模的顶部上的第一部分和硬掩模的相对侧壁上的第二部分和第三部分。 该方法还包括去除间隔层的第一部分; 去除硬面膜; 并且使用间隔层的第二部分和第三部分作为掩模来对第一硬掩模层进行图案化。

    Coupling mechanism interposed between a seat and a back of a chair to prevent a reclining motion of the back from tilting the seat
    10.
    发明授权
    Coupling mechanism interposed between a seat and a back of a chair to prevent a reclining motion of the back from tilting the seat 失效
    插入在座椅和椅子背部之间的联接机构，以防止背部倾斜运动使座椅倾斜

    公开(公告)号：US07614697B1

    公开(公告)日：2009-11-10

    申请号：US12213219

    申请日：2008-06-17

    申请人： Chih-Yu Lai

    发明人： Chih-Yu Lai

    IPC分类号： A47C3/026 ,  A47C1/024 ,  A47C1/032 ,  A47C1/038

    CPC分类号： A47C1/03294 ,  A47C1/03255 ,  A47C1/03266 ,  A47C1/03272

    摘要： A chair has a coupling mechanism between a seat and a back, which includes a joining member, and a coupling member; the seat has two opposite front and two opposite rear ears on a bottom; the joining member is secured on a supporting tube for the seat, and has two opposite sloping slots on each end, and intermediate adjustment slots; the connecting member has a front fixing hole, and a rear sloping slot; the joining member, the connecting member, and the seat are joined together with a first shaft passed through the front ears and the front sloping slots, with a second shaft passed through the rear ears and all of the rear sloping slots; a third shaft is passed through the adjustment slots and the fixing hole; the connecting member is further pivoted to the joining member at a middle portion; the back is joined to the connecting member.

    摘要翻译： 椅子具有在座椅和背部之间的联接机构，其包括接合构件和联接构件; 座位在底部有两个相对的前部和两个相对的后耳朵; 接合构件被固定在座椅的支撑管上，并且在每个端部具有两个相对的倾斜槽和中间调节槽; 连接构件具有前固定孔和后倾斜槽; 接合构件，连接构件和座椅通过穿过前耳和前倾斜槽的第一轴连接在一起，第二轴穿过后耳和所有后倾斜槽; 第三轴穿过调节槽和固定孔; 连接构件在中间部分进一步枢转到接合构件; 背面连接到连接构件。