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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20110195550A1

    公开(公告)日：2011-08-11

    申请号：US13007096

    申请日：2011-01-14

    申请人： Chong-Kwang CHANG ,  Sung-Hon Chi ,  Hong-Jae Shin ,  Yong-Jin Chung ,  Young-Mook Oh ,  Ju-Beom Yi

    发明人： Chong-Kwang CHANG ,  Sung-Hon Chi ,  Hong-Jae Shin ,  Yong-Jin Chung ,  Young-Mook Oh ,  Ju-Beom Yi

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/823864 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.

    摘要翻译： 一种制造半导体器件的方法，所述方法包括提供半导体衬底; 在所述半导体衬底上形成栅极图案，使得所述栅极图案包括栅极电介质层和牺牲栅电极; 在半导体衬底和栅极图案上形成蚀刻停止层和电介质层; 去除介电层的部分以暴露蚀刻停止层; 在所述蚀刻停止层上执行蚀刻工艺以暴露所述牺牲栅电极; 去除所述牺牲栅电极以形成沟槽; 在包括沟槽的半导体衬底上形成金属层; 去除所述金属层的部分以暴露所述介电层; 以及对所述金属层执行到预定目标的回蚀处理。

    METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE 审中-公开
    形成半导体器件精细图案的方法

    公开(公告)号：US20110201202A1

    公开(公告)日：2011-08-18

    申请号：US13007071

    申请日：2011-01-14

    申请人： Chong-Kwang CHANG ,  Young-Mook OH ,  Seo-Woo NAM ,  Woo-Cheol JEON ,  Ju-Beom YI ,  Myung-Joo LEE

    发明人： Chong-Kwang CHANG ,  Young-Mook OH ,  Seo-Woo NAM ,  Woo-Cheol JEON ,  Ju-Beom YI ,  Myung-Joo LEE

    IPC分类号： H01L21/3105

    CPC分类号： H01L21/0337 ,  H01L21/0338

    摘要： A method of forming fine patterns of a semiconductor device, the method including providing a patternable layer; forming a plurality of first photoresist layer patterns on the patternable layer; forming an interfacial layer on the patternable layer and the plurality of first photoresist layer patterns; forming a planarization layer on the interfacial layer; forming a plurality of second photoresist layer patterns on the planarization layer; forming a plurality of planarization layer patterns using the plurality of second photoresist layer patterns; and forming a plurality of layer patterns using the plurality of planarization layer patterns and the plurality of first photoresist layer patterns.

    摘要翻译： 一种形成半导体器件的精细图案的方法，所述方法包括提供可图案化层; 在所述可图案层上形成多个第一光致抗蚀剂层图案; 在所述可图案层和所述多个第一光致抗蚀剂层图案上形成界面层; 在界面层上形成平坦化层; 在平坦化层上形成多个第二光致抗蚀剂层图案; 使用所述多个第二光致抗蚀剂层图案形成多个平坦化图案; 以及使用所述多个平坦化层图案和所述多个第一光致抗蚀剂层图案形成多个层图案。

    METHOD OF FORMING A CONTACT HOLE AND APPARATUS FOR PERFORMING THE SAME
    3.
    发明申请
    METHOD OF FORMING A CONTACT HOLE AND APPARATUS FOR PERFORMING THE SAME 审中-公开
    形成接触孔的方法和实施该接触孔的装置

    公开(公告)号：US20130023127A1

    公开(公告)日：2013-01-24

    申请号：US13476381

    申请日：2012-05-21

    申请人： Chong-Kwang CHANG ,  Young-Mook OH ,  Jung-Hoon LEE ,  Hak-Yoon AHN

    发明人： Chong-Kwang CHANG ,  Young-Mook OH ,  Jung-Hoon LEE ,  Hak-Yoon AHN

    IPC分类号： H01L21/3065 ,  C23F1/08

    CPC分类号： H01L21/76802 ,  H01J37/32091 ,  H01J37/32165 ,  H01J37/32522 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144

    摘要： A method of forming a contact hole includes loading a substrate into a plasma chamber, the substrate including an etch stop layer, an insulation interlayer, a mask layer and a photoresist pattern sequentially disposed thereon, applying a DC voltage to an upper electrode and applying a first high frequency power and a second high frequency power to a lower electrode to generate plasma in the chamber, the first frequency power and second high frequency powers having different frequency levels, supplying a reaction gas to the chamber to etch the mask layer and the insulation interlayer, wherein the chamber is maintained at a temperature of 100° C. to 200° C.; and etching the etch stop layer to form a contact hole

    摘要翻译： 形成接触孔的方法包括将基板装载到等离子体室中，所述基板包括顺序地设置在其上的蚀刻停止层，绝缘中间层，掩模层和光致抗蚀剂图案，向上电极施加直流电压， 第一高频功率和第二高频功率到下电极以在腔室中产生等离子体，第一频率功率和第二高频功率具有不同的频率水平，向腔室供应反应气体以蚀刻掩模层和绝缘体 中间层，其中所述室保持在100℃至200℃的温度。 并蚀刻蚀刻停止层以形成接触孔