公开(公告)号：US06702637B2

公开(公告)日：2004-03-09

申请号：US10048148

申请日：2002-01-25

申请人： Choon-Sup Lee ,  Jae-Duk Lee ,  Chul-Hi Han

发明人： Choon-Sup Lee ,  Jae-Duk Lee ,  Chul-Hi Han

IPC分类号： H01J912

CPC分类号： H01J1/304 ,  H01J1/3042 ,  H01J9/022

摘要： The present invention relates to a method of forming a small gap using CMP and a method for manufacturing a lateral FED. In the present invention, a small gap is determined by the thickness of an oxide film, and so uniform small gaps of about 100 Å that have been impossible to attain with the art of prior lithography can be formed with repeatability. Prior lateral field emission devices have the problem of repeatability in forming a gap for field emission because they are fabricated by means of a thermal stress method or an electrical stress method. But if the method of forming a small gap according to the present invention is used to fabricate a lateral FED, a FED can be made that has low voltage drive and high current drive characteristics and uniform field emission characteristics.

摘要翻译： 本发明涉及使用CMP形成小间隙的方法以及制造横向FED的方法。 在本发明中，通过氧化膜的厚度来确定小的间隙，并且可以以重现性形成与现有的光刻技术无法达到的均匀的大约的小间隙。 现有的横向场致发射装置在形成场发射间隙时具有重复性的问题，因为它们是通过热应力法或电应力法制造的。 但是，如果使用根据本发明的形成小间隙的方法来制造横向FED，则可以制造具有低电压驱动和高电流驱动特性以及均匀场致发射特性的FED。

公开(公告)号：US06033925A

公开(公告)日：2000-03-07

申请号：US864551

申请日：1997-05-27

申请人： Chul-Hi Han ,  Hi-Deok Lee ,  Jae-Kwan Kim

发明人： Chul-Hi Han ,  Hi-Deok Lee ,  Jae-Kwan Kim

IPC分类号： H01L21/308 ,  H01L21/02 ,  H01L21/20 ,  H01L21/3063 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L21/2007 ,  H01L21/3063 ,  H01L21/76251 ,  Y10S438/977

摘要： The present invention relates to a method for manufacturing a semiconductor wafer having a SOI wafer-like structure which is prepared on a silicon substrate by electrochemical etching, and an active-driven liquid crystal display employing the semiconductor wafer as a pixel switching wafer. In accordance with the method for manufacturing the SOI-type semiconductor wafer, a wafer having a good electrical insulation property, low leakage current and small parasitic capacity, like a SOI wafer, can be prepared, by employing a silicon substrate which is cheaper than the SOI substrate.

摘要翻译： 本发明涉及一种通过电化学蚀刻在硅衬底上制备具有SOI晶片状结构的半导体晶片的制造方法以及采用半导体晶片作为像素转换晶片的主动驱动液晶显示器。 根据SOI型半导体晶片的制造方法，可以通过采用比SOI晶片便宜的硅基板来制备具有良好的电绝缘性，低漏电流和小的寄生电容的晶片，如SOI晶片 SOI衬底。

公开(公告)号：US06747625B1

公开(公告)日：2004-06-08

申请号：US09628040

申请日：2000-07-27

申请人： Chul-Hi Han ,  Hoon-Ju Chung ,  Seung-Woo Lee

发明人： Chul-Hi Han ,  Hoon-Ju Chung ,  Seung-Woo Lee

IPC分类号： G09G336

CPC分类号： G09G3/3688 ,  G09G2310/027

摘要： A digital driving circuit for a liquid crystal display which sequentially receives and displays n-bit digital video information from a data bus on a bit basis. The digital driving circuit comprises a first data latch for sequentially storing the digital video information from the data bus on a bit basis, a shift register for synchronizing a latching operation of the first data latch with bit positions of the digital video information from the data bus, a second data latch for storing the digital video information stored in the first data latch temporarily before digital/analog conversion, and a digital/analog converter for sequentially converting the digital video information stored in the second data latch into analog signals on a bit basis. The digital driving circuit is able to sequentially process bit information of digital video information to reduce the number of data bus lines for loading the bit information thereon and the number of data catches arranged vertically to a column direction. Therefore, the driving circuit can be significantly reduced in its occupying width, thereby making it possible to make the display higher in density.

摘要翻译： 一种用于液晶显示器的数字驱动电路，其依次从数据总线接收并显示n位数字视频信息。 数字驱动电路包括第一数据锁存器，用于以数据总线顺序地存储来自数据总线的数字视频信息;移位寄存器，用于使第一数据锁存器的锁存操作与来自数据总线的数字视频信息的位位置同步 ，用于在数字/模拟转换之前临时存储存储在第一数据锁存器中的数字视频信息的第二数据锁存器，以及用于将存储在第二数据锁存器中的数字视频信息顺序地转换成模拟信号的数/模转换器 。 数字驱动电路能够顺序地处理数字视频信息的位信息，以减少用于加载其中的位信息的数据总线的数量和垂直于列方向布置的数据捕获的数量。 因此，驱动电路的占据宽度可以显着降低，从而可以使显示器的密度更高。

公开(公告)号：US6064590A

公开(公告)日：2000-05-16

申请号：US130801

申请日：1998-08-07

申请人： Chul-Hi Han ,  Sung-Hoi Hur

发明人： Chul-Hi Han ,  Sung-Hoi Hur

IPC分类号： H01L27/11 ,  G11C14/00 ,  G11C16/04

CPC分类号： G11C14/00

摘要： A non-volatile static random access memory device configured by adding a floating gate type metal oxide semiconductor device to an SRAM including a pair of access elements respectively switched on and off in accordance with the state of a signal on an address line and adapted to establish a data transfer path between memory cell and associated negative and positive data lines, and a pair of inverters respectively coupled to the access elements, thereby allowing the SRAM to exhibit non-volatile memory characteristics. The floating gate type MOS device has a silicon substrate, a tunneling oxide film formed over the silicon substrate, a floating gate formed on the tunneling oxide film, an oxide film formed over the floating gate, a control gate formed over the oxide film, and a source and a drain respectively formed in an upper surface of the silicon substrate at both sides of the control gate. The source and drain of the floating gate type MOS device are electrically connected at the source and drain thereof to the input terminals of the inverters of the SRAM, respectively, so that it provides non-volatile memory characteristics to the SRAM by virtue of a difference in threshold voltage caused by charge stored in the floating gate thereof. This non-volatile SRAM device has a high density while exhibiting high-speed operation characteristics.

摘要翻译： 一种非易失性静态随机存取存储器件，通过根据地址线上的信号的状态将浮栅型金属氧化物半导体器件添加到包括分别接通和关断的一对存取元件的SRAM，并适于建立 存储器单元和相关联的负和正数据线之间的数据传输路径，以及分别耦合到访问元件的一对反相器，从而允许SRAM呈现非易失性存储器特性。 浮栅型MOS器件具有硅衬底，在硅衬底上形成的隧道氧化膜，在隧道氧化膜上形成的浮栅，形成在浮栅上的氧化膜，形成在氧化物膜上的控制栅，以及 分别形成在控制栅极两侧的硅衬底的上表面中的源极和漏极。 浮栅型MOS器件的源极和漏极分别在源极和漏极之间电连接到SRAM的反相器的输入端，使得其通过差异向SRAM提供非易失性存储器特性 在由其存储在其浮动栅极中的电荷引起的阈值电压中。 这种非易失性SRAM器件具有高密度，同时具有高速操作特性。

公开(公告)号：US5700699A

公开(公告)日：1997-12-23

申请号：US405501

申请日：1995-03-16

申请人： Chul-Hi Han ,  Choong-Ki Kim ,  Jung-Yeal Lee ,  Kil-Hwan Oh

发明人： Chul-Hi Han ,  Choong-Ki Kim ,  Jung-Yeal Lee ,  Kil-Hwan Oh

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/84

CPC分类号： H01L29/66757 ,  H01L21/28158 ,  H01L29/4908

摘要： A method for fabricating the polycrystal silicon TFT under a low temperature which has an improved electron mobility, comprises the steps of forming an oxide film on a substrate, depositing a polycrystal silicon on the oxide film and patterning the polycrystal silicon so that source and drain regions and a channel region remain, growing a gate insulating layer on the patterned polycrystal silicon by ECR plasma thermal oxidation, depositing a material for a gate on the whole surface and removing the material and the gate insulating layer in portions except for a gate region to form the gate, and performing ion implantation on the exposed areas of the polycrystal silicon to form the source and drain regions.

摘要翻译： 在低温下制造具有改善的电子迁移率的多晶硅TFT的方法包括以下步骤：在衬底上形成氧化膜，在氧化物膜上沉积多晶硅并使多晶硅图形化，使得源极和漏极区域 并且保持沟道区域，通过ECR等离子体热氧化在图案化多晶硅上生长栅极绝缘层，在整个表面上沉积用于栅极的材料，并除去栅极区域以外的部分去除材料和栅极绝缘层以形成 并且在多晶硅的暴露区域上进行离子注入以形成源区和漏区。