公开(公告)号：US06702637B2

公开(公告)日：2004-03-09

申请号：US10048148

申请日：2002-01-25

申请人： Choon-Sup Lee ,  Jae-Duk Lee ,  Chul-Hi Han

发明人： Choon-Sup Lee ,  Jae-Duk Lee ,  Chul-Hi Han

IPC分类号： H01J912

CPC分类号： H01J1/304 ,  H01J1/3042 ,  H01J9/022

摘要： The present invention relates to a method of forming a small gap using CMP and a method for manufacturing a lateral FED. In the present invention, a small gap is determined by the thickness of an oxide film, and so uniform small gaps of about 100 Å that have been impossible to attain with the art of prior lithography can be formed with repeatability. Prior lateral field emission devices have the problem of repeatability in forming a gap for field emission because they are fabricated by means of a thermal stress method or an electrical stress method. But if the method of forming a small gap according to the present invention is used to fabricate a lateral FED, a FED can be made that has low voltage drive and high current drive characteristics and uniform field emission characteristics.

摘要翻译： 本发明涉及使用CMP形成小间隙的方法以及制造横向FED的方法。 在本发明中，通过氧化膜的厚度来确定小的间隙，并且可以以重现性形成与现有的光刻技术无法达到的均匀的大约的小间隙。 现有的横向场致发射装置在形成场发射间隙时具有重复性的问题，因为它们是通过热应力法或电应力法制造的。 但是，如果使用根据本发明的形成小间隙的方法来制造横向FED，则可以制造具有低电压驱动和高电流驱动特性以及均匀场致发射特性的FED。

公开(公告)号：US20090283811A1

公开(公告)日：2009-11-19

申请号：US12385042

申请日：2009-03-30

申请人： Jae-Duk Lee ,  Choong-Ho Lee

发明人： Jae-Duk Lee ,  Choong-Ho Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825

摘要： A flash memory device and/or methods of forming the flash memory device are provided, the flash memory device including a charge storage gate, a gate pattern over the charge storage gate, and a charge storage metal layer disposed between a side surface of the charge storage gate and the gate pattern. The methods include forming a preliminary charge storage gate pattern and forming a metal layer over a side surface of the preliminary charge storage gate pattern.

摘要翻译： 提供闪速存储器件和/或形成闪存器件的方法，闪速存储器件包括电荷存储栅极，电荷存储栅极上的栅极图案，以及设置在电荷侧表面之间的电荷存储金属层 存储门和门模式。 所述方法包括形成初步电荷存储栅极图案并在初步电荷存储栅极图案的侧表面上形成金属层。

公开(公告)号：US20050006695A1

公开(公告)日：2005-01-13

申请号：US10726768

申请日：2003-12-03

申请人： Jae-Duk Lee ,  Dong-gun Park ,  Jeong-Hyuk Choi

发明人： Jae-Duk Lee ,  Dong-gun Park ,  Jeong-Hyuk Choi

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7883

摘要： In a floating gate memory cell including a floating gate separated from an active region by a tunnel isolation region, a first one of the active region and the floating gate comprises a portion that protrudes towards a second one of the active region and the floating gate. In some embodiments, the protruding portion tapers toward the second one of the active region and the floating gate. The tunnel insulation layer may be narrowed at the protruding portion. Protruding portions may be formed on both the floating gate and the active region.

摘要翻译： 在包括通过隧道隔离区域与有源区域分离的浮动栅极的浮动栅极存储单元中，有源区域和浮置栅极中的第一个包括朝向有源区域和浮置栅极中的第二个突出的部分。 在一些实施例中，突出部分朝向有源区域和浮动栅极中的第二个逐渐变细。 隧道绝缘层可以在突出部分变窄。 突出部分可以形成在浮动栅极和有源区域两者上。

公开(公告)号：US07214588B2

公开(公告)日：2007-05-08

申请号：US11247814

申请日：2005-10-11

申请人： Jae-Duk Lee ,  Dong-gun Park ,  Jeong-Hyuk Choi

发明人： Jae-Duk Lee ,  Dong-gun Park ,  Jeong-Hyuk Choi

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7883

摘要： In a floating gate memory cell including a floating gate separated from an active region by a tunnel isolation region, a first one of the active region and the floating gate comprises a portion that protrudes towards a second one of the active region and the floating gate. In some embodiments, the protruding portion tapers toward the second one of the active region and the floating gate. The tunnel insulation layer may be narrowed at the protruding portion. Protruding portions may be formed on both the floating gate and the active region.

摘要翻译： 在包括通过隧道隔离区域与有源区域分离的浮动栅极的浮动栅极存储单元中，有源区域和浮置栅极中的第一个包括朝向有源区域和浮置栅极中的第二个突出的部分。 在一些实施例中，突出部分朝向有源区域和浮动栅极中的第二个逐渐变细。 隧道绝缘层可以在突出部分变窄。 突出部分可以形成在浮动栅极和有源区域两者上。

公开(公告)号：US20060124988A1

公开(公告)日：2006-06-15

申请号：US11291142

申请日：2005-11-30

申请人： Sung-Hoi Hur ,  Jung-Dal Choi ,  Kyeong-Tae Kim ,  Jong-Ho Park ,  Jae-Duk Lee ,  Ki-Nam Kim

发明人： Sung-Hoi Hur ,  Jung-Dal Choi ,  Kyeong-Tae Kim ,  Jong-Ho Park ,  Jae-Duk Lee ,  Ki-Nam Kim

IPC分类号： H01L21/82 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor memory device is fabricated by forming an active region protruding from a semiconductor substrate, forming an isolation layer on the substrate adjacent opposing sidewalls of the active region, and forming a floating gate electrode on a surface of the active region between the opposing sidewalls thereof. The floating gate electrode is formed to extend beyond edges of the surface of the active region onto the isolation layer. A surface of the floating gate electrode adjacent the active region defines a plane, and the isolation layer is confined between the plane and the substrate. A control gate electrode is formed on a surface of the floating gate electrode opposite the active region. The control gate electrode may be formed to extend along sidewalls of the floating gate electrode towards the substrate beyond the plane defined by the surface of the floating gate electrode adjacent the active region. Related devices are also discussed.

摘要翻译： 半导体存储器件通过形成从半导体衬底突出的有源区域形成，在邻近有源区域的相对侧壁的衬底上形成隔离层，以及在其相对侧壁之间的有源区域的表面上形成浮栅电极 。 浮栅电极被形成为延伸超过有源区表面的边缘到隔离层上。 邻近有源区的浮栅电极的表面限定了一个平面，隔离层被限制在平面和衬底之间。 控制栅电极形成在浮动栅电极的与有源区相对的表面上。 控制栅电极可以被形成为沿着浮置栅电极的侧壁朝着衬底延伸超过由邻近有源区的浮栅的表面限定的平面。 还讨论了相关设备。

公开(公告)号：US06998669B2

公开(公告)日：2006-02-14

申请号：US10726768

申请日：2003-12-03

申请人： Jae-Duk Lee ,  Dong-gun Park ,  Jeong-Hyuk Choi

发明人： Jae-Duk Lee ,  Dong-gun Park ,  Jeong-Hyuk Choi

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7883

摘要： In a floating gate memory cell including a floating gate separated from an active region by a tunnel isolation region, a first one of the active region and the floating gate comprises a portion that protrudes towards a second one of the active region and the floating gate. In some embodiments, the protruding portion tapers toward the second one of the active region and the floating gate. The tunnel insulation layer may be narrowed at the protruding portion. Protruding portions may be formed on both the floating gate and the active region.

摘要翻译： 在包括通过隧道隔离区域与有源区域分离的浮动栅极的浮动栅极存储单元中，有源区域和浮置栅极中的第一个包括朝向有源区域和浮置栅极中的第二个突出的部分。 在一些实施例中，突出部分朝向有源区域和浮动栅极中的第二个逐渐变细。 隧道绝缘层可以在突出部分变窄。 突出部分可以形成在浮动栅极和有源区域两者上。

公开(公告)号：US06905927B2

公开(公告)日：2005-06-14

申请号：US10680813

申请日：2003-10-07

申请人： Jae-Young Ahn ,  Bong-Hyun Kim ,  Jae-Duk Lee ,  Man-Sug Kang

发明人： Jae-Young Ahn ,  Bong-Hyun Kim ,  Jae-Duk Lee ,  Man-Sug Kang

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A semiconductor device and method of production are disclosed, the method including forming a preliminary gate electrode on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and performing a re-oxidation process for curing damage of the semiconductor substrate and/or a sidewall of the conductive layer pattern, when the preliminary gate electrode is formed by forming an oxide layer on an outer surface of the preliminary gate electrode and on the semiconductor substrate, by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased; and the semiconductor device comprising a preliminary gate electrode formed on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and a re-oxidized semiconductor substrate and/or a sidewall of the conductive layer pattern, with damage cured therein by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased.

摘要翻译： 公开了一种半导体器件和制造方法，该方法包括在半导体衬底上形成初步栅电极，该初步栅电极包括栅极氧化层图案和层叠在栅氧化层图案上的导电层图案， 用于固化半导体衬底和/或导电层图案的侧壁的损伤的氧化工艺，当通过在预选栅电极的外表面上和在半导体衬底上形成氧化物层而形成预备栅电极时， 氧气和含氯气体，同时抑制栅极氧化物层图案的厚度增加; 并且所述半导体器件包括形成在半导体衬底上的初步栅电极，所述预选栅电极包括栅极氧化物层图案和层叠在所述栅极氧化物层图案上的导电层图案，以及再氧化半导体衬底和/或侧壁 的导电层图案，其中通过供给氧气和含氯气体同时抑制其中的腐蚀而同时抑制栅极氧化物层图案的厚度增加。

公开(公告)号：US20150004777A1

公开(公告)日：2015-01-01

申请号：US14272237

申请日：2014-05-07

申请人： Kanamori Kohji ,  Young-Woo Park ,  Jin-Taek Park ,  Jae-Duk Lee

发明人： Kanamori Kohji ,  Young-Woo Park ,  Jin-Taek Park ,  Jae-Duk Lee

IPC分类号： H01L21/02

CPC分类号： H01L21/02672 ,  H01L21/02532 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： Methods of fabricating a vertical cell semiconductor device including forming a hole passing through a stacked structure of alternating insulating and sacrificial layers on a substrate, forming an amorphous silicon layer conforming to an inner wall of the hole, forming a silicon region on the amorphous silicon layer, and metal induced crystallizing the amorphous silicon layer via the silicon region to form a single-crystalline channel structure in the hole.

摘要翻译： 制造垂直单元半导体器件的方法包括在衬底上形成通过交替的绝缘层和牺牲层的层叠结构的孔，形成与孔的内壁一致的非晶硅层，在非晶硅层上形成硅区 并且金属诱导通过硅区域结晶非晶硅层以在孔中形成单晶通道结构。

公开(公告)号：US06660587B2

公开(公告)日：2003-12-09

申请号：US10205987

申请日：2002-07-26

申请人： Jae-Young Ahn ,  Bong-Hyun Kim ,  Jae-Duk Lee ,  Man-Sug Kang

发明人： Jae-Young Ahn ,  Bong-Hyun Kim ,  Jae-Duk Lee ,  Man-Sug Kang

IPC分类号： H01L21336

CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A semiconductor device and method of production are disclosed, the method including forming a preliminary gate electrode on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and performing a re-oxidation process for curing damage of the semiconductor substrate and/or a sidewall of the conductive layer pattern, when the preliminary gate electrode is formed by forming an oxide layer on an outer surface of the preliminary gate electrode and on the semiconductor substrate, by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased; and the semiconductor device comprising a preliminary gate electrode formed on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and a re-oxidized semiconductor substrate and/or a sidewall of the conductive layer pattern, with damage cured therein by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased.

公开(公告)号：US09318329B2

公开(公告)日：2016-04-19

申请号：US14272237

申请日：2014-05-07

申请人： Kanamori Kohji ,  Young-Woo Park ,  Jin-Taek Park ,  Jae-Duk Lee

发明人： Kanamori Kohji ,  Young-Woo Park ,  Jin-Taek Park ,  Jae-Duk Lee

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L21/02672 ,  H01L21/02532 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： Methods of fabricating a vertical cell semiconductor device including forming a hole passing through a stacked structure of alternating insulating and sacrificial layers on a substrate, forming an amorphous silicon layer conforming to an inner wall of the hole, forming a silicon region on the amorphous silicon layer, and metal induced crystallizing the amorphous silicon layer via the silicon region to form a single-crystalline channel structure in the hole.

摘要翻译： 制造垂直单元半导体器件的方法包括在衬底上形成通过交替的绝缘层和牺牲层的层叠结构的孔，形成与孔的内壁一致的非晶硅层，在非晶硅层上形成硅区 并且金属诱导通过硅区域结晶非晶硅层以在孔中形成单晶通道结构。