公开(公告)号：US06346904B1

公开(公告)日：2002-02-12

申请号：US09635765

申请日：2000-08-11

申请人： Christophe Gaillard ,  Marc Wingender ,  Stéphane Le Tual

发明人： Christophe Gaillard ,  Marc Wingender ,  Stéphane Le Tual

IPC分类号： H03M112

CPC分类号： H03M1/445

摘要： A signal aliasing circuit that can be used especially to make a series interpolation cell of an interpolation analog-digital converter comprises two pairs of differential arms powered by one and the same current source connected to a first power supply terminal, each pair comprising two transistors, the transistors of one pair being parallel-connected with the transistors of the other pair. Each group of two parallel-connected transistors is connected by a respective common resistor to a second power supply terminal, the two outputs of the aliasing circuit being the combined collectors of the two groups of parallel-connected transistors. The disclosed device can be applied especially to converters whose architecture comprises what is known as a series interpolation part requiring high precision.

摘要翻译： 可以特别用于制作插值模拟数字转换器的串联插补单元的信号混叠电路包括由连接到第一电源端子的同一个电流源供电的两对差分臂，每对包含两个晶体管， 一对的晶体管与另一对的晶体管并联连接。 两个并联连接的晶体管的每组由相应的公共电阻器连接到第二电源端子，混叠电路的两个输出是两组并联晶体管的组合集电极。 所公开的装置可以特别应用于其架构包括所谓的要求高精度的串联插补部件的转换器。

公开(公告)号：US06658446B1

公开(公告)日：2003-12-02

申请号：US09647537

申请日：2000-10-02

申请人： Laurent Simony ,  Stéphane Le Tual ,  Marc Wingender

发明人： Laurent Simony ,  Stéphane Le Tual ,  Marc Wingender

IPC分类号： G06F750

CPC分类号： G06F7/5013

摘要： A chainable adder receives bits (A, B, C) to give complementary sum outputs (SO, SO*) and carry outputs (CO, CO*). A first stage has differential pairs (P1, P2, P3) receiving bits (A, B, C), respectively, and complements (A*, B*, C*), respectively. The pairs have common output arms and are powered by an identical current (I). First and second output arms include resistors (R1, R2, R3) and (R4, R5, R6), respectively, connected-in-series to a reference potential (M). The resistors define intermediate nodes (A1, A2, A3) in the first arm, (B1, B2, B3) in the second arm. Carry outputs are taken at nodes (A2, B2). A second stage has differential pairs (P4, P5, P6) whose inputs are connected to nodes (A1, B3) for pair (P4), (A2, B2) for pair (P5), and (A3, B1) for pair (P6). Pairs (P4, P6) each have a common arm with the pair (P5) and a non-common arm. The sum outputs are constituted by a combination, according to an “OR” function, of logic states on the non-common arm of one of pairs (P4, P6) and on the common arm of another of pairs (P4, P6).

摘要翻译： 可连接的加法器接收比特（A，B，C）以给出补码和输出（SO，SO *）和进位输出（CO，CO *），第一级具有差分对（P1，P2，P3） ，B，C）和补充（A *，B *，C *）。 这些对具有共同的输出臂并由相同的电流（I）供电。 第一和第二输出臂分别包括与参考电位（M）串联连接的电阻器（R1，R2，R3）和（R4，R5，R6）。 电阻器定义第二臂中的中间节点（A1，A2，A3），（B1，B2，B3）。 在节点（A2，B2）处进行进位输出。第二级具有差分对（P4，P5，P6），其输入连接到用于对（P4），（A2，B2）的对（P4），（A2，B2） P5）和（A3，B1）对（P6）。 对（P4，P6）每个都有一对共同的臂（P5）和一个非共同的臂。 总和输出由一对（P4，P6）和另一对（P4，P6）的公共臂上的逻辑状态的组合来构成。

公开(公告)号：US07515085B2

公开(公告)日：2009-04-07

申请号：US11994183

申请日：2006-06-23

申请人： Francois Bore ,  Sandrine Bruel ,  Marc Wingender

发明人： Francois Bore ,  Sandrine Bruel ,  Marc Wingender

IPC分类号： H03M1/36

CPC分类号： H03F3/45744 ,  H03F3/45085 ,  H03F3/45596 ,  H03F2203/45032 ,  H03F2203/45371 ,  H03M1/0607 ,  H03M1/141 ,  H03M1/362

摘要： The invention relates to integrated circuits comprising a set of identical differential pairs of two transistors each (T1, T2; T3, T4) one receiving a variable voltage (Vinp, Vinn) at its base and the other receiving a fixed reference voltage (Vrefp, Vrefn). In order to reduce the dispersion of the offset voltages of said differential pairs, it is provided that the transistor (T2, T4) that receives a fixed reference voltage has an emitter surface at least twice as large as the transistor (T1, T3) that receives a variable voltage at its base. Application to signal folding circuits and to analog-to-digital converters using differential pairs of transistors.

摘要翻译： 本发明涉及集成电路，其包括一组相同的差分对的两个晶体管，每个晶体管（T1，T2; T3，T4）在其基极处接收可变电压（Vinp，Vinn），另一个接收固定参考电压（Vrefp， Vrefn）。 为了减小所述差分对的偏移电压的偏差，接收固定参考电压的晶体管（T2，T4）的发射极表面至少是晶体管（T1，T3）的两倍， 在其底部接收可变电压。 应用信号折叠电路和使用差分晶体管对的模数转换器。

公开(公告)号：US06236348B1

公开(公告)日：2001-05-22

申请号：US09508106

申请日：2000-03-17

申请人： François Bore ,  Marc Wingender

发明人： François Bore ,  Marc Wingender

IPC分类号： H03M112

CPC分类号： H03M1/368

摘要： Signal-folding converters which establish two so-called fold analogue signals, whose curves of variation as a function of a voltage Vin to be converted cross over at multiple points. The architecture establishes n pairs of voltages varying with Vin and crossing over for regularly distributed values Vin=Vk. At least two current routing circuits are provided, each of which possesses at least three pairs of inputs and at least two outputs including a direct output and an inverse output. The direct outputs, linked together, provide a folded signal SR; the inverse outputs provide a complementary folded signal SRb. Each routing circuit receives three voltage pairs of rank k−1, k, and k+1 and includes a current source supplying a group of branches arranged as a tree-like structure. The apportioning of the current in each branchoff depends on the voltage pairs of rank k−1, k, and k+1, and the direct and inverse outputs of the circuit are tapped respectively from two different branches of the last stage of the tree-like structure.

摘要翻译： 信号折叠转换器，其建立两个所谓的折叠模拟信号，其变化曲线作为要转换的电压Vin的函数在多个点交叉。 该体系结构建立了n对电压变化的电压，并跨越规则分布的值Vin = Vk。 提供至少两个电流路由电路，每个电路具有至少三对输入和包括直接输出和反相输出的至少两个输出。 连接在一起的直接输出提供折叠信号SR; 反向输出提供互补折叠信号SRb。 每个路由电路接收秩k-1，k和k + 1的三个电压对，并且包括提供被布置为树状结构的一组分支的电流源。 每个分支中的电流分配取决于秩k-1，k和k + 1的电压对，电路的直接和反向输出分别从树形结构的最后一个阶段的两个不同的分支中抽出， 像结构。

公开(公告)号：US20080211705A1

公开(公告)日：2008-09-04

申请号：US11994183

申请日：2006-06-23

申请人： Francois Bore ,  Sandrine Bruel ,  Marc Wingender

发明人： Francois Bore ,  Sandrine Bruel ,  Marc Wingender

IPC分类号： H03M1/36

CPC分类号： H03F3/45744 ,  H03F3/45085 ,  H03F3/45596 ,  H03F2203/45032 ,  H03F2203/45371 ,  H03M1/0607 ,  H03M1/141 ,  H03M1/362

摘要： The invention relates to integrated circuits comprising a set of identical differential pairs of two transistors each (T1, T2; T3, T4) one receiving a variable voltage (Vinp, Vinn) at its base and the other receiving a fixed reference voltage (Vrefp, Vrefn). In order to reduce the dispersion of the offset voltages of said differential pairs, it is provided that the transistor (T2, T4) that receives a fixed reference voltage has an emitter surface at least twice as large as the transistor (T1, T3) that receives a variable voltage at its base. Application to signal folding circuits and to analog-to-digital converters using differential pairs of transistors.

摘要翻译： 本发明涉及集成电路，其包括一组相同的差分对的两个晶体管，每个晶体管（T 1，T 2; T 3，T 4）在其基极处接收可变电压（Vinp，Vinn），而另一个接收固定参考 电压（Vrefp，Vrefn）。 为了减小所述差分对的偏移电压的偏差，提供了接收固定参考电压的晶体管（T 2，T 4）的发射极表面至少是晶体管的两倍（T 1， T 3）在其基地接收可变电压。 应用信号折叠电路和使用差分晶体管对的模数转换器。

公开(公告)号：US6166674A

公开(公告)日：2000-12-26

申请号：US885959

申请日：1997-06-30

申请人： Marc Wingender ,  Stephane Le Tual

发明人： Marc Wingender ,  Stephane Le Tual

IPC分类号： H03M1/06 ,  H03M1/16 ,  H03M1/44 ,  H03M1/34 ,  H03M1/62

CPC分类号： H03M1/204 ,  H03M1/0682 ,  H03M1/0695 ,  H03M1/168

摘要： Disclosed is an analog to digital converter with several cascade-connected interpolation and selection circuits. The function of an interpolation circuit is to produce five pairs of output signals from three pairs of input signals and select three pairs from among the five pairs to apply them to the next stage. Each pair comprises two interpolation signals that vary symmetrically and monotonically as a function of the voltage Vin, the signals of one pair being equal when the voltage Vin is equal to a reference voltage associated with this pair. There are five reference voltage associated with the five pairs. Among these five reference voltages, the three reference voltages (and therefore also the three corresponding pairs of signals) that most closely surround the input voltage Vin are selected. The reference voltages are increasingly closer together as the operation progresses in the succession of cascade-connected stages. The signals used to select the pairs of signals are used in a decoder that gives the bits of the analog-digital conversion.

摘要翻译： 公开了具有几个级联连接的内插和选择电路的模数转换器。 内插电路的功能是从三对输入信号产生五对输出信号，并从五对中选择三对，将其应用于下一级。 每对包括两个插值信号，它们作为电压Vin的函数对称地和单调地变化，当电压Vin等于与该对相关联的参考电压时，一对信号相等。 有五个参考电压与五对相关联。 在这五个参考电压中，选择最接近于输入电压Vin的三个参考电压（因此也是三个对应的信号对）。 随着连续级联连接阶段的操作进行，参考电压越来越近。 用于选择信号对的信号用于给出模数转换位的解码器。

公开(公告)号：US5471210A

公开(公告)日：1995-11-28

申请号：US151852

申请日：1993-11-15

申请人： Marc Wingender ,  Stephane Le Tual

发明人： Marc Wingender ,  Stephane Le Tual

IPC分类号： H03M1/14 ,  H03M1/36 ,  H03M1/34

CPC分类号： H03M1/147 ,  H03M1/365

摘要： The invention concerns precision analogue-digital converters. For the fine conversion, supplying the low order bits (B0 to Bk) for an analogue voltage Vin to be converted, three ordinary differential amplifiers (ADA, ADB, ADC) are used connected to three voltage references VR(i-1), VR(i), VR(i+1). These three amplifiers supply differential output voltages (VAa, VAb, VBa, VBb, VCa, VCb) that vary as a function of Vin according to normal transfer functions for differential amplifiers. Intersection points of these various transfer curves are detected in interpolation circuits (firstly CIT1, then CIT2, etc). These intersection points are used as intermediate voltage references between the main references. Comparators (CMP0 . . . CMPk), placed at the output of interpolation circuits supply bits (B0 to Bk) indicating the value of Vin with respect to each of these intermediate references.

摘要翻译： 本发明涉及精密模数转换器。 为了精细转换，为了要转换的模拟电压Vin提供低位（B0到Bk），三个普通差分放大器（ADA，ADB，ADC）被连接到三个电压基准VR（i-1），VR （i），VR（i + 1）。 这三个放大器根据差分放大器的正常传输函数提供根据Vin变化的差分输出电压（VAa，VAb，VBa，VBb，VCa，VCb）。 在插补电路（首先是CIT1，然后CIT2等）中检测这些各种传输曲线的交点。 这些交点用作主参考之间的中间参考电压。 位于内插电路的输出端的比较器（CMP0，...，CMPk）提供指示Vin相对于这些中间参考值中的每一个的值的位（B0至Bk）。

公开(公告)号：US5444447A

公开(公告)日：1995-08-22

申请号：US174419

申请日：1993-12-28

申请人： Marc Wingender

发明人： Marc Wingender

IPC分类号： H03M1/16 ,  H03M1/36 ,  H03M1/14

CPC分类号： H03M1/165 ,  H03M1/365

摘要： The disclosure relates to analog-digital converters. It is sought to limit the power consumption and obtain a better compromise among the different performance characteristics of the computer. In a general structure of a converter there are, firstly, a coarse converter for the most significant bits and, secondly, a fine converter for the least significant bits. One of them, generally, the fine converter, has differential amplifiers [AD(1) to AD(N)]receiving the voltage to be converted (Ve) and a reference voltage. It is proposed to place sample-and-hold circuits [EB(1) to EB(N)] at output of these differential amplifiers and to eliminate the sample-and-hold circuit that is often placed upline with respect to these amplifiers.

摘要翻译： 本公开涉及模数转换器。 旨在限制功耗，并在计算机的不同性能特征之间获得更好的折衷。 在转换器的一般结构中，首先是用于最高有效位的粗转换器，其次是用于最低有效位的精细转换器。 其中一个通常是精细转换器，具有接收待转换电压（Ve）和参考电压的差分放大器[AD（1）至AD（N）]。 建议在这些差分放大器的输出处放置采样保持电路[EB（1）至EB（N）]，并消除通常相对于这些放大器放置的取样和保持电路。