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    Gage surface scraper
    3.
    发明申请
    Gage surface scraper 失效
    量规表面刮刀

    公开(公告)号：US20050211474A1

    公开(公告)日：2005-09-29

    申请号：US10809644

    申请日：2004-03-25

    申请人： Don Nguyen ,  Terry Koltermann ,  Gregory Ricks ,  Mark Morris ,  Chris McCarty ,  Chih Lin

    发明人： Don Nguyen ,  Terry Koltermann ,  Gregory Ricks ,  Mark Morris ,  Chris McCarty ,  Chih Lin

    IPC分类号： E21B10/08

    CPC分类号： E21B10/08

    摘要： A gage scraper cleans mud from the gage surface of a rotary cone of a drill bit. The bit has a body having at least one leg depending therefrom, a bearing pin secured to each leg, and a rotary cutting cone mounted to the bearing pin. The cone has a conical gage surface. The gage scraper mounts on the inside of each leg and protrudes from the leg toward the cone into close proximity with the gage surface.

    摘要翻译： 量具刮刀从钻头的旋转锥体的量规表面清除泥浆。 所述钻头具有至少一个从其悬挂的支脚的主体，固定到每个支腿的支承销以及安装在所述支承销上的旋转切割锥。 锥体具有锥形表面。 量规刮刀安装在每个腿的内侧，并从腿部朝向锥体突出，与计量表面紧密接近。

    CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxiliary bipolar transistor
    6.
    发明授权
    CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxiliary bipolar transistor 失效
    CMOS集成电路架构结合深注入发射极区域形成辅助双极晶体管

    公开(公告)号：US06350640B1

    公开(公告)日：2002-02-26

    申请号：US08276290

    申请日：1994-07-18

    申请人： Robert T. Fuller ,  Chris McCarty ,  John T. Gasner ,  Michael D. Church

    发明人： Robert T. Fuller ,  Chris McCarty ,  John T. Gasner ,  Michael D. Church

    IPC分类号： H01L218238

    CPC分类号： H01L27/0623

    摘要： To program a CMOS memory, an auxiliary bipolar transistor is formed in a P-well adjacent to the P-well of an NMOS device of the CMOS memory, the auxiliary transistor being capable of forcing a large magnitude current through a fusible link, so as to program the electronic state of the CMOS memory cell into a prescribed binary (1/0) condition. A separate implant mask for the emitter region of the auxiliary transistor allows the geometry and impurity concentration profile of the emitter region to be tailored by a deep dual implant, so that the impurity concentration of the emitter region is not decreased, and yields a reduced base width for the auxiliary transistor to provide a relatively large current gain to blow the fuse, while allowing the doping parameters of the source/drain regions of the CMOS structure to be separately established to prevent thyristor latch-up.

    摘要翻译： 为了编程CMOS存储器，辅助双极晶体管形成在与CMOS存储器的NMOS器件的P阱相邻的P阱中，辅助晶体管能够通过可熔链路强制大幅度电流，因此 将CMOS存储单元的电子状态编程为规定的二进制（1/0）条件。 用于辅助晶体管的发射极区域的单独的注入掩模允许通过深度双注入来调整发射极区域的几何形状和杂质浓度分布，使得发射极区域的杂质浓度不降低，并且产生降低的基极 宽度用于提供相对较大的电流增益来熔断熔丝，同时允许分别建立CMOS结构的源/漏区的掺杂参数以防止晶闸管闭锁。

    N Contact compensation technique
    9.
    发明授权
    N Contact compensation technique 失效
    N接触补偿技术

    公开(公告)号：US4553315A

    公开(公告)日：1985-11-19

    申请号：US597060

    申请日：1984-04-05

    申请人： Chris McCarty

    发明人： Chris McCarty

    IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/768 ,  H01L29/08 ,  H01L21/28

    CPC分类号： H01L29/0847 ,  H01L21/26513 ,  H01L21/28525 ,  H01L21/76885 ,  Y10S148/083

    摘要： The contact for N channel devices in a CMOS process is formed by ion implanting N-type impurities through contact apertures in the dielectric layer to a depth less than the source and drain regions and a layer of conductive material is applied without intermediate etching and delineated.

    摘要翻译： CMOS工艺中的N沟道器件的接触是通过将介电层中的接触孔离子注入N型杂质形成的深度小于源极和漏极区域的深度，并且在没有中间蚀刻和描绘的情况下施加一层导电材料。