公开(公告)号：USH986H

公开(公告)日：1991-11-05

申请号：US363747

申请日：1989-06-09

申请人： Christopher F. Codella ,  Nivo Rovedo ,  Seiki Ogura

发明人： Christopher F. Codella ,  Nivo Rovedo ,  Seiki Ogura

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/28132 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7835

摘要： A field effect transistor of asymmetrical structure comprises: a semiconductor substrate of first conductivity type; source and drain regions of second conductivity type disposed in a surface of the substrate and spaced apart by a channel region; and a single, lightly doped extension of the drain region into the channel, the extension being of the second conductivity type and of a lower dopant concentration than the drain region. The transistor can further beneficially comprise a halo region of the first conductivity type in the substrate generally surrounding only the source region.

公开(公告)号：US4855246A

公开(公告)日：1989-08-08

申请号：US247140

申请日：1988-09-21

申请人： Christopher F. Codella ,  Seiki Ogura

发明人： Christopher F. Codella ,  Seiki Ogura

IPC分类号： H01L21/338 ,  H01L29/08 ,  H01L29/10 ,  H01L29/812

CPC分类号： H01L29/66878 ,  H01L29/0891 ,  H01L29/1075 ,  H01L29/812 ,  Y10S148/082 ,  Y10S148/14 ,  Y10S148/161

摘要： Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. In one embodiment, the device consists of a shallow n.sup.- active channel region formed on a GaAs substrate, a Schottky gate overlying the n.sup.- region and highly doped and deep n.sup.+ source and drain regions formed on either side of the gate. In the channel region between the gate edges and the source/drain are positioned n-type source/drain extensions which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels.In a second embodiment, p-type pockets are provided under the source/drain extensions to better control the device threshold voltage and further reduce the channel length.In terms of the method of fabrication of the first embodiment, starting with a GaAs substrate an n.sup.- semiconductor layer is formed in the device active region. Next, a Schottky gate is formed in direct contact with the n.sup.- layer. Next, a dielectric layer is deposited and reactive ion etched (RIE), forming gate sidewalls. Then, n-type source/drain extensions are formed followed by repetition of the dielectric layer deposition and RIE to enlarge the gate sidewalls. Finally, source/drain are implanted.To form the second structure a p-type ion implantation is accomplished prior to or after the source/drain extension forming step to form the deep p-type pockets.

摘要翻译： 公开了一种自对准GaAs，轻掺杂漏极金属 - 半导体场效应晶体管。 在一个实施例中，器件由形成在GaAs衬底上的浅n-有源沟道区，覆盖在n-区上的肖特基栅极和形成在栅极的任一侧上的高度掺杂和深的n +源极和漏极区组成。 在栅极边缘和源极/漏极之间的沟道区域中放置有具有中间深度和掺杂浓度的n型源极/漏极延伸，以最小化器件串联电阻，抑制短沟道效应并允许通道长度降低到亚微米级。 在第二实施例中，在源极/漏极扩展器下面设置p型凹穴，以更好地控制器件阈值电压并进一步减小沟道长度。 就第一实施例的制造方法而言，从GaAs衬底开始，在器件有源区中形成n-半导体层。 接下来，形成与n层直接接触的肖特基栅极。 接下来，沉积介电层并反应离子蚀刻（RIE），形成栅极侧壁。 然后，形成n型源极/漏极延伸部，随后重复介质层沉积和RIE以扩大栅极侧壁。 最后，植入源/漏。 为了形成第二结构，在源极/漏极扩展形成步骤之前或之后实现p型离子注入以形成深p型凹穴。

公开(公告)号：US4636822A

公开(公告)日：1987-01-13

申请号：US644830

申请日：1984-08-27

申请人： Christopher F. Codella ,  Seiki Ogura

发明人： Christopher F. Codella ,  Seiki Ogura

IPC分类号： H01L21/265 ,  H01L21/338 ,  H01L29/08 ,  H01L29/10 ,  H01L29/812 ,  H01L29/80 ,  H01L29/48

CPC分类号： H01L29/66878 ,  H01L29/0891 ,  H01L29/1075 ,  H01L29/812 ,  Y10S257/90

摘要： Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. In one embodiment, the device consists of a shallow n.sup.- active channel region formed on a GaAs substrate, a Schottky gate overlying the n.sup.- region and highly doped and deep n.sup.+ source and drain regions formed on either side of the gate. In the channel region between the gate edges and the source/drain are positioned n-type source/drain extensions which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels.In a second embodiment, p-type pockets are provided under the source/drain extensions to better control the device threshold voltage and further reduce the channel length.In terms of the method of fabrication of the first embodiment, starting with a GaAs substrate an n.sup.- semiconductor layer is formed in the device active region. Next, a Schottky gate is formed in direct contact with the n.sup.- layer. Next, a dielectric layer is deposited and reactive ion etched (RIE), forming gate sidewalls. Then, n-type source/drain extensions are formed followed by repetition of the dielectric layer deposition and RIE to enlarge the gate sidewalls. Finally, source/drain are implanted.To form the second structure a p-type ion implantation is accomplished prior to or after the source/drain extension forming step to form the deep p-type pockets.

摘要翻译： 公开了一种自对准GaAs，轻掺杂漏极金属 - 半导体场效应晶体管。 在一个实施例中，器件由形成在GaAs衬底上的浅n-有源沟道区，覆盖在n-区上的肖特基栅极和形成在栅极的任一侧上的高度掺杂和深的n +源极和漏极区组成。 在栅极边缘和源极/漏极之间的沟道区域中放置有具有中间深度和掺杂浓度的n型源极/漏极延伸，以最小化器件串联电阻，抑制短沟道效应并允许通道长度降低到亚微米级。 在第二实施例中，在源极/漏极扩展器下面设置p型凹穴，以更好地控制器件阈值电压并进一步减小沟道长度。 就第一实施例的制造方法而言，从GaAs衬底开始，在器件有源区中形成n-半导体层。 接下来，形成与n层直接接触的肖特基栅极。 接下来，沉积介电层并反应离子蚀刻（RIE），形成栅极侧壁。 然后，形成n型源极/漏极延伸部，随后重复介质层沉积和RIE以扩大栅极侧壁。 最后，植入源/漏。 为了形成第二结构，在源极/漏极扩展形成步骤之前或之后实现p型离子注入以形成深p型凹穴。

公开(公告)号：US07088684B2

公开(公告)日：2006-08-08

申请号：US09906596

申请日：2001-07-16

申请人： Marcos N. Novaes ,  Christopher F. Codella

发明人： Marcos N. Novaes ,  Christopher F. Codella

IPC分类号： H04L12/44

CPC分类号： H04L45/22 ,  H04L12/185 ,  H04L12/1854 ,  H04L12/1877 ,  H04L45/00 ,  H04L45/16

摘要： Methods and arrangements for repositioning at least one node in a distributed network. Upon detection of a failed node in the network, subscription information relating to each direct child node of the failed node is retained at each direct child node.

公开(公告)号：US20130346614A1

公开(公告)日：2013-12-26

申请号：US13533164

申请日：2012-06-26

申请人： Aaron K. Baughman ,  Linda M. Boyer ,  Christopher F. Codella ,  Richard L. Darden ,  William G. Dubyak ,  Arnold Greenland

发明人： Aaron K. Baughman ,  Linda M. Boyer ,  Christopher F. Codella ,  Richard L. Darden ,  William G. Dubyak ,  Arnold Greenland

IPC分类号： G06F15/173

CPC分类号： G06F9/5083

摘要： A workload associated with a task is assessed with respect to each of a plurality of computing paradigms offered by a cloud computing environment. Adaptive learning is employed by maintaining a table of Q-values corresponding to the computing paradigms and the workload is distributed according to a ratio of Q-values. The Q-values may be adjusted responsive to a performance metric and/or a value, reward, and/or decay function. The workload is then assigned to available computing paradigms to be performed with improved utilization of resources.

摘要翻译： 相对于由云计算环境提供的多个计算范例中的每一个来评估与任务相关联的工作量。 通过维护对应于计算范例的Q值表，采用自适应学习，并根据Q值的比例分配工作量。 可以响应于性能度量和/或价值，奖励和/或衰减功能来调整Q值。 然后将工作负载分配给可用的计算范例，以更好地利用资源来执行。

公开(公告)号：US08793381B2

公开(公告)日：2014-07-29

申请号：US13533164

申请日：2012-06-26

申请人： Aaron K. Baughman ,  Linda M. Boyer ,  Christopher F. Codella ,  Richard L. Darden ,  William G. Dubyak ,  Arnold Greenland

发明人： Aaron K. Baughman ,  Linda M. Boyer ,  Christopher F. Codella ,  Richard L. Darden ,  William G. Dubyak ,  Arnold Greenland

IPC分类号： G06F15/173

CPC分类号： G06F9/5083

摘要： A workload associated with a task is assessed with respect to each of a plurality of computing paradigms offered by a cloud computing environment. Adaptive learning is employed by maintaining a table of Q-values corresponding to the computing paradigms and the workload is distributed according to a ratio of Q-values. The Q-values may be adjusted responsive to a performance metric and/or a value, reward, and/or decay function. The workload is then assigned to available computing paradigms to be performed with improved utilization of resources.

摘要翻译： 相对于由云计算环境提供的多个计算范例中的每一个来评估与任务相关联的工作量。 通过维护对应于计算范例的Q值表，采用自适应学习，并根据Q值的比例分配工作量。 可以响应于性能度量和/或价值，奖励和/或衰减功能来调整Q值。 然后将工作负载分配给可用的计算范例，以更好地利用资源来执行。

公开(公告)号：US06804818B1

公开(公告)日：2004-10-12

申请号：US09302043

申请日：1999-04-29

申请人： Christopher F. Codella ,  Donald F. Ferguson ,  Ignacio Silva-Lepe

发明人： Christopher F. Codella ,  Donald F. Ferguson ,  Ignacio Silva-Lepe

IPC分类号： G06F944

CPC分类号： G06F9/541

摘要： In accordance with the present invention, methods are included, which may be implemented by employing a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for anonymously integrating an object oriented software component with message oriented clients. A method is included for anonymously integrating object-oriented software components and message-oriented clients wherein a first object-oriented component performs the steps of performing invocations which are serviced by one of message-oriented clients and object-oriented components and servicing the invocations which are performed by one of the message-oriented clients and the object-oriented components such that the first object-oriented component is unaware that the invocations are performed and serviced by one of the message-oriented clients and the object-oriented components.

摘要翻译： 根据本发明，可以通过采用机器可读的程序存储装置来实现方法，其有形地体现了可由机器执行的指令程序，以执行匿名整合面向对象的面向软件组件与消息导向的方法步骤 客户。 包括用于匿名集成面向对象的软件组件和面向消息的客户端的方法，其中第一面向对象的组件执行执行由面向消息的客户端之一和面向对象的组件服务的调用的步骤，以及为调用服务 由面向消息的客户端和面向对象的组件中的一个执行，使得第一面向对象的组件不知道调用由面向消息的客户端和面向对象的组件之一执行和服务。