公开(公告)号：US20060208937A1

公开(公告)日：2006-09-21

申请号：US11374233

申请日：2006-03-13

Applicant: Christopher Hurrell ,  Colin Price

Inventor： Christopher Hurrell ,  Colin Price

IPC: H03M1/12

CPC classification number: H03M1/144 ,  H03M1/0643 ,  H03M1/0678 ,  H03M1/0695 ,  H03M1/1019 ,  H03M1/46

Abstract: An analog to digital converter comprising at least two analog to digital conversion engines and a controller for controlling the operation of the analog to digital conversion engines such that during a first phase of an analog to digital conversion process the engines collaborate such that a plurality of bits can be determined during a single trial step; and during a second phase of the analog to digital conversion the conversion engines work independently; and the controller receives the outputs of at least one of the conversion engines and processes them to provide an output word.

Abstract translation: 一种模数转换器，包括至少两个模数转换引擎和用于控制模数转换引擎的操作的控制器，使得在模数转换过程的第一阶段期间，引擎协作使得多个位 可以在单个试用阶段确定; 并且在模数转换的第二阶段期间，转换引擎独立工作; 并且控制器接收至少一个转换引擎的输出并处理它们以提供输出字。

公开(公告)号：US06724239B2

公开(公告)日：2004-04-20

申请号：US10156613

申请日：2002-05-28

Applicant: Colin Price ,  Mark Stephen Power

Inventor： Colin Price ,  Mark Stephen Power

IPC: G05F110

CPC classification number: H03K17/063 ,  H02M3/07

Abstract: A voltage boost circuit includes a boost capacitor; a charge circuit for charging in the charging mode the boost capacitor to a supply voltage, the charging circuit including a charging MOS switch interconnected between the supply voltage and one terminal of the boost capacitor and a back gate isolation circuit connected to the back gate of the charging MOS switch and including a first switch for connecting the back gate to the supply voltage for reverse biasing the back gate in the charging mode and the second switch for connecting the back gate to the one terminal of the boost capacitor for reverse biasing the back gate in the boost mode to prevent charge loss from the boost capacitor; and a boost bias voltage and a boost switch for connecting the second terminal of the boost capacitor to the boost bias voltage in the boost mode.

Abstract translation: 升压电路包括升压电容器; 充电电路，用于在所述充电模式下将所述升压电容器充电到电源电压，所述充电电路包括在所述电源电压和所述升压电容器的一个端子之间互连的充电MOS开关和连接到所述升压电容器的所述背栅极的背栅绝缘电路; 充电MOS开关并且包括用于将背栅极连接到用于在充电模式中反向偏置背栅的电源电压的第一开关和用于将后栅极连接到升压电容器的一个端子的第二开关，用于反向偏置背栅极 在升压模式下，防止升压电容器的电荷损失; 以及用于在升压模式下将升压电容器的第二端子连接到升压偏置电压的升压偏置电压和升压开关。

公开(公告)号：US5619204A

公开(公告)日：1997-04-08

申请号：US394709

申请日：1995-02-27

Applicant: Michael Byrne ,  Colin Price ,  John Reidy ,  Simon Smith

Inventor： Michael Byrne ,  Colin Price ,  John Reidy ,  Simon Smith

IPC: H03M1/00 ,  H03M1/12

CPC classification number: H03M1/002 ,  H03M1/12

Abstract: An IC chip having an analog-to-digital converter together with control circuitry for effecting switchover between normal-power mode and low-power mode. The control circuitry includes a first D-type flip-flop with reset which receives on its "D" input a continuous high signal; on its differential clock inputs the flip-flop receives complementary logic signals derived from the "conversion start" (CONVST) signal applied to one pin of an 8-pin chip. In normal mode, the CONVST signal is a short pulse having an initial negative-going (falling) leading edge, and the flip-flop responds to that leading edge by producing a high Q output (CONVEN). This signals the A/D converter to carry out a conversion. In low-power mode, the CONVST short pulse is positive. The subsequent negative-going (falling) trailing edge of the pulse activates the flip-flop to cause its Q output to go high and turn on the A/D converter. The control circuitry includes a second D-type flip-flop (this one with set) which receives on its D input the CONVST signal. The Q output. of the second flip-flop generates a mode switchover control signal (designated SLEEPB). During low-power mode, established by the use of positive-going CONVST pulses, the low CONVEN signal at the end of conversion clocks the second flip-flop to sample CONVST on its D input, thereby causing the Q output of the second flip-flop (SLEEPB) to go low and switch the A/D converter into low-power status.

Abstract translation: 具有模数转换器和控制电路的IC芯片，用于在正常功率模式和低功率模式之间进行切换。 控制电路包括具有复位的第一D型触发器，其在其“D”输入端接收连续的高信号; 在其差分时钟输入端，触发器接收从施加到8引脚芯片的一个引脚的“转换开始”（CONVST）信号导出的互补逻辑信号。 在正常模式下，CONVST信号是具有初始负向（下降）前沿的短脉冲，并且触发器通过产生高Q输出（CONVEN）来响应该前沿。 这将通知A / D转换器进行转换。 在低功耗模式下，CONVST短脉冲为正。 脉冲的后续负（下降）后沿激活触发器，使其Q输出变为高电平，并打开A / D转换器。 该控制电路包括一个第二D型触发器（这个具有一组的触发器），其在其D输入端接收CONVST信号。 Q输出。 的第二触发器产生模式切换控制信号（指定为SLEEPB）。 在通过使用正向CONVST脉冲建立的低功耗模式期间，转换结束时的低CONVEN信号使第二触发器在其D输入上对CONVST进行采样，从而导致第二触发器的Q输出， 触发器（SLEEPB）变为低电平，并将A / D转换器切换到低功耗状态。

公开(公告)号：US07928744B2

公开(公告)日：2011-04-19

申请号：US12326552

申请日：2008-12-02

Applicant: Colin Price ,  Steven Boyle ,  Asif Ahmad

Inventor： Colin Price ,  Steven Boyle ,  Asif Ahmad

IPC: G05F1/00

CPC classification number: G01R19/1659 ,  G01R31/31932 ,  G01R31/362 ,  G01R31/3658 ,  G01R35/00

Abstract: A measuring apparatus including a self test function, the circuit comprising a capacitor; first to fourth switches; a test signal injector; at least one comparator having a signal input and a reference input the first switch being interposed between a first plate of the capacitor and a first input node, the second switch being interposed between a second plate of the capacitor and a second input node, the third switch being interposed between the first plate of the capacitor and the signal input of the comparator and the fourth switch being interposed between the second plate of the capacitor and a voltage reference, wherein the self test function comprises the steps of i) operating the signal injector to produce a first signal representative of an out of range voltage for an expected voltage difference between the first and second input nodes, and using the signal to cause the at least one comparator to place its output in an error state, and to charge the capacitor to the out of range voltage, ii) isolating the capacitor from the signal injector and voltage reference, and connecting the capacitor between the first and second input nodes such that the voltage stored on the capacitor is overwritten by the voltage difference between the first and second nodes, and iii) and reconnecting the capacitor to the comparator and monitoring the comparator's output.

Abstract translation: 一种包括自检功能的测量装置，所述电路包括电容器; 第一至第四开关; 测试信号注射器; 具有信号输入和参考输入的至少一个比较器，所述第一开关插入所述电容器的第一板和第一输入节点之间，所述第二开关插入在所述电容器的第二板和第二输入节点之间，所述第三开关 开关插入在电容器的第一板和比较器的信号输入端之间，第四开关插在电容器的第二板和电压基准之间，其中自检功能包括以下步骤：i）操作信号注入器 以产生表示第一和第二输入节点之间的期望电压差超出范围电压的第一信号，并且使用该信号使至少一个比较器将其输出置于误差状态，并为电容器充电 超出范围电压，ii）将电容器与信号注入器和参考电压隔离，并将电容器连接在第一和第二电容器之间 输入节点，使得存储在电容器上的电压被第一和第二节点之间的电压差覆盖，以及iii）并且将电容器重新连接到比较器并监视比较器的输出。

公开(公告)号：US07181635B2

公开(公告)日：2007-02-20

申请号：US10723464

申请日：2003-11-26

Applicant: Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

Inventor： Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

IPC: G06F1/26

CPC classification number: H03M1/004 ,  G06F1/3209 ,  H03M1/002 ,  H03M1/46 ,  H03M1/462 ,  H03M1/70 ,  H04W52/0287 ,  Y02D70/122

Abstract: A method for placing a device in a selected mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. The selected operating mode may be a reduced power consumption mode, for example, or another operating mode of the device, such as a daisy-chain mode of operation, or a mode that accommodates programming of analog input range.

Abstract translation: 一种用于将设备放置在所选择的操作模式中的方法。 该方法包括以下步骤：将设备选择信号初始化为第一逻辑状态，在第二逻辑状态中断言设备选择信号，并在第一用户控制的时间窗口内将设备选择信号返回到第一逻辑状态。 还描述了一种装置，其包括用于检测设备选择输入和时钟输入处的逻辑状态转换的装置，以及用于响应于时钟输入处的预定数量的逻辑状态转换来改变设备的工作模式的装置，发生在逻辑 设备选择输入的状态转换。 所选择的操作模式可以是诸如菊花链操作模式的降低的功耗模式，例如或设备的另一操作模式，或者是适应模拟输入范围的编程的模式。

公开(公告)号：US20050035895A1

公开(公告)日：2005-02-17

申请号：US10723464

申请日：2003-11-26

Applicant: Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

Inventor： Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

IPC: G06F1/32 ,  H03M1/00 ,  H03M1/12 ,  H03M1/42 ,  H03M1/46 ,  H03M1/70 ,  H04M1/73 ,  H03M1/34

CPC classification number: H03M1/004 ,  G06F1/3209 ,  H03M1/002 ,  H03M1/46 ,  H03M1/462 ,  H03M1/70 ,  H04W52/0287 ,  Y02D70/122

Abstract: A method for placing a device in a selected mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. The selected operating mode may be a reduced power consumption mode, for example, or another operating mode of the device, such as a daisy-chain mode of operation, or a mode that accommodates programming of analog input range.

Abstract translation: 一种用于将设备放置在所选择的操作模式中的方法。 该方法包括以下步骤：将设备选择信号初始化为第一逻辑状态，在第二逻辑状态中断言设备选择信号，并在第一用户控制的时间窗口内将设备选择信号返回到第一逻辑状态。 还描述了一种装置，其包括用于检测设备选择输入和时钟输入处的逻辑状态转换的装置，以及用于响应于时钟输入处的预定数量的逻辑状态转换来改变设备的工作模式的装置，发生在逻辑 设备选择输入的状态转换。 所选择的操作模式可以是诸如菊花链操作模式的降低的功耗模式，例如或设备的另一操作模式，或者是适应模拟输入范围的编程的模式。

公开(公告)号：US06681332B1

公开(公告)日：2004-01-20

申请号：US09523610

申请日：2000-03-13

Applicant: Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

Inventor： Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

IPC: G06F132

CPC classification number: G06F1/3209 ,  H03M1/002

Abstract: A method for placing a device in a reduced power-consumption mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first predetermined time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input.

Abstract translation: 一种用于将设备放置在降低的功耗操作模式中的方法。 该方法包括以下步骤：将设备选择信号初始化为第一逻辑状态，以第二逻辑状态断言设备选择信号，并在第一预定时间窗口内将设备选择信号返回到第一逻辑状态。 还描述了一种装置，其包括用于检测设备选择输入和时钟输入处的逻辑状态转换的装置，以及用于响应于时钟输入处的预定数量的逻辑状态转换来改变设备的工作模式的装置，发生在逻辑 设备选择输入的状态转换。

公开(公告)号：US5422583A

公开(公告)日：1995-06-06

申请号：US207856

申请日：1994-03-08

Applicant: John Blake ,  Anthony Gribben ,  Colin Price

Inventor： John Blake ,  Anthony Gribben ,  Colin Price

IPC: G11C27/02 ,  H03K17/687 ,  H03K17/00

CPC classification number: H03K17/687 ,  G11C27/024 ,  H03K2217/0018

Abstract: An improved back gate switched sample and hold circuit includes a sample and hold channel including a sample switch having a back gate and a storage element; a back gate circuit for controlling the back gate of the sample switch; and a first attenuator circuit for scaling the input signal from a low impedance source for delivery to the sample switch and a second attenuator circuit responsive to the input signal from the low impedance source to independently drive the back gate circuit and isolate any distortion of the input signal in the back gate circuit from affecting the input signal in said sample and hold channel.

Abstract translation: 改进的背栅开关采样和保持电路包括采样和保持通道，其包括具有后栅极和存储元件的采样开关; 用于控制采样开关的背栅的背栅电路; 以及第一衰减器电路，用于缩放来自低阻抗源的输入信号以传送到采样开关;以及第二衰减器电路，响应于来自低阻抗源的输入信号，独立地驱动背栅电路并隔离输入的任何失真 后门电路中的信号影响所述采样和保持通道中的输入信号。