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公开(公告)号：US07123104B2
公开(公告)日：2006-10-17
申请号：US10644542
申请日：2003-08-20
IPC分类号： H03B5/24 , G01R19/00 , H03K17/296
CPC分类号： G01R19/252 , G01R19/0092
摘要： The present invention is directed to a system and method for measuring a current in an integrated circuit comprising measuring a first output count from a first voltage controlled oscillator (VCO) using a first measurement voltage, simultaneously measuring a second output count from a second VCO using a second measurement voltage, and calculating the current in the integrated circuit using a voltage proportional to a difference between the first and second output counts.
摘要翻译： 本发明涉及一种用于测量集成电路中的电流的系统和方法，包括使用第一测量电压测量来自第一压控振荡器（VCO）的第一输出计数，同时使用第二测量电压测量来自第二VCO的第二输出计数 第二测量电压，并且使用与第一和第二输出计数之间的差成比例的电压来计算集成电路中的电流。
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公开(公告)号：US08037445B2
公开(公告)日：2011-10-11
申请号：US10644625
申请日：2003-08-20
CPC分类号： G01R31/2884 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： An apparatus comprising an integrated circuit on a VLSI die, and an embedded micro-controller constructed on the VLSI die, the micro-controller adapted to monitor and control the VLSI environment to optimize the integrated circuit operation. Another embodiment of the invention is directed to a method for monitoring and controlling an integrated circuit comprising providing an embedded micro-controller on a same VLSI die as the integrated circuit, monitoring and controlling a VLSI environment of the integrated circuit with the embedded micro-controller.
摘要翻译： 一种包括VLSI管芯上的集成电路和在VLSI管芯上构建的嵌入式微控制器的装置，该微控制器适用于监测和控制VLSI环境以优化集成电路操作。 本发明的另一个实施例涉及一种用于监测和控制集成电路的方法，包括在与集成电路相同的VLSI管芯上提供嵌入式微控制器，利用嵌入式微控制器监视和控制集成电路的VLSI环境 。
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3.发明授权公开(公告)号：US07091796B2
公开(公告)日：2006-08-15
申请号：US10644559
申请日：2003-08-20
IPC分类号： H03B5/04
CPC分类号： G01R35/005 , H03M1/1038 , H03M1/60
摘要： A method for calibrating a voltage controlled oscillator (VCO) comprising applying a plurality of known voltages to the input of a VCO, monitoring, for each of the voltages, an output count from the VCO over a set interval, and storing the output counts for each voltage. Also disclosed is a system for calibrating a voltage controlled oscillator (VCO) comprising a plurality of known voltages, wherein the known voltage are connectable to the VCO, and a controller coupled to the output of the VCO, wherein the controller maintains a calibration table of VCO output counts for selected voltage inputs.
摘要翻译： 一种用于校准压控振荡器（VCO）的方法，包括将多个已知电压施加到VCO的输入端，对于每个电压，在设定的间隔内监视来自VCO的输出计数，并将输出计数存储在 每个电压。 还公开了一种用于校准包括多个已知电压的压控振荡器（VCO）的系统，其中已知电压可连接到VCO，以及耦合到VCO的输出的控制器，其中控制器保持校准表 所选电压输入的VCO输出计数。
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4.发明授权Method for measuring integrated circuit processor power demand and associated system 有权集成电路处理器电力需求和相关系统的测量方法公开(公告)号：US06954706B2
公开(公告)日：2005-10-11
申请号：US10644376
申请日：2003-08-20
IPC分类号： G01R19/00 , G01R21/133 , G01R31/28 , G01R31/317 , G01R35/00 , G06F19/00 , H01L23/34
CPC分类号： G01R31/31721 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for measuring integrated circuit processor power demand comprises calibrating one or more voltage controlled oscillators for use as ammeters, calibrating a calibration current source, wherein the calibration current source draws current through a inherent resistance, calibrating the inherent resistance, and interleaving said calibrations in time with calculating the processor power demand using a voltage that is measured across the inherent resistance.
摘要翻译： 一种用于测量集成电路处理器功率需求的系统和方法包括校准一个或多个压控振荡器，用作电流表，校准校准电流源，其中校准电流源通过固有电阻来吸取电流，校准固有电阻，并交织所述 使用在固有电阻上测量的电压计算处理器功率需求时，可以及时校准。
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公开(公告)号：US07844838B2
公开(公告)日：2010-11-30
申请号：US11589573
申请日：2006-10-30
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： Devices and methods for managing power on a module are disclosed herein. In one embodiment, a module comprises a first die; a second die; and a power manager. The power manager monitors the power requirements of the first die and the second die and allocates power to the first die and the second die based on the power requirements.
摘要翻译： 本文公开了用于管理模块电源的设备和方法。 在一个实施例中，模块包括第一管芯; 第二个死亡 和电源经理。 电源管理器监视第一管芯和第二管芯的功率要求，并根据电源要求为第一管芯和第二管芯分配电源。
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公开(公告)号：US07148755B2
公开(公告)日：2006-12-12
申请号：US10648570
申请日：2003-08-26
CPC分类号： H03L7/087 , H03L7/07 , H03L7/0992
摘要： A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The system also includes a controller that provides a control signal to adjust the operating voltage based on adjustments to the frequency of the clock signal.
摘要翻译： 可用于实现电压调整（例如，用于集成电路）的系统和方法。 在一个实施例中，该系统包括提供具有基于工作电压而变化的频率的时钟信号的频率发生器。 该系统还包括控制器，其提供控制信号以根据对时钟信号的频率的调整来调整工作电压。
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公开(公告)号：US20080104428A1
公开(公告)日：2008-05-01
申请号：US11589573
申请日：2006-10-30
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： Devices and methods for managing power on a module are disclosed herein. In one embodiment, a module comprises a first die; a second die; and a power manager. The power manager monitors the power requirements of the first die and the second die and allocates power to the first die and the second die based on the power requirements.
摘要翻译： 本文公开了用于管理模块电源的设备和方法。 在一个实施例中，模块包括第一管芯; 第二个死亡 和电源经理。 电源管理器监视第一管芯和第二管芯的功率要求，并根据电源要求为第一管芯和第二管芯分配电源。
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8.发明授权Systems and methods for maintaining performance of an integrated circuit within a working power limit 失效用于在工作功率极限内保持集成电路性能的系统和方法公开(公告)号：US07661003B2
公开(公告)日：2010-02-09
申请号：US11040394
申请日：2005-01-21
CPC分类号： G06F1/3203 , G06F1/28
摘要： Systems and methods for maintaining performance of an integrated circuit are disclosed. One embodiment of a system may comprise a working power limit evaluator that determines a working power limit as a function of at least one performance factor associated with variations that affect performance of the integrated circuit. The system may further comprise a power management system that varies power of the integrated circuit based on the working power limit and an actual power of the integrated circuit to maintain a substantially constant performance.
摘要翻译： 公开了用于维持集成电路性能的系统和方法。 系统的一个实施例可以包括工作功率限制评估器，其确定作为与影响集成电路的性能的变化相关联的至少一个性能因素的函数的工作功率极限。 该系统还可以包括功率管理系统，其基于工作功率极限和集成电路的实际功率来改变集成电路的功率以维持基本上恒定的性能。
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9.发明授权Multiple input bit-line detection with phase stealing latch in a memory design 有权多输入位线检测与存储器设计中的相位锁存器公开(公告)号：US06278627B1
公开(公告)日：2001-08-21
申请号：US09504138
申请日：2000-02-15
申请人： Kevin Liao , Joel D. Lamb , Christopher A. Poirier
发明人： Kevin Liao , Joel D. Lamb , Christopher A. Poirier
IPC分类号： G11C506
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1051
摘要： A method and apparatus are provided for sensing and temporarily latching data signals from memory cells. According to one embodiment, data signals are sensed from memory cells and temporarily latched on an output signal. During a first phase of a clock cycle, multiple input bit-lines are precharged. Subsequently, a discharged input bit-line is sensed during a second phase of the clock cycle. Responsive to the sensing step, the output signal is set to a first state and maintained for at least one clock cycle. According to another embodiment, a multiple input bit-line detecting circuit includes multiple input bit-lines, precharge logic, and output logic. The multiple input bit-lines are configured to be coupled to a bit-line hierarchy of a memory device. The precharge logic is coupled to each of the input bit-lines and is configured to precharge each of the input bit-lines during a first phase of a clock cycle. The output logic is operatively coupled to the multiple input bit-lines to set an output signal to a first state and maintain the first state on the output signal for at least one clock cycle in response to one or more of the input bit-lines being discharged.
摘要翻译： 提供了用于感测和临时锁存来自存储器单元的数据信号的方法和装置。 根据一个实施例，从存储器单元感测数据信号并临时锁存在输出信号上。 在时钟周期的第一阶段，多个输入位线被预充电。 随后，在时钟周期的第二阶段期间感测到放电的输入位线。 响应于感测步骤，输出信号被设置为第一状态并保持至少一个时钟周期。 根据另一实施例，多输入位线检测电路包括多个输入位线，预充电逻辑和输出逻辑。 多个输入位线被配置为耦合到存储器件的位线层级。 预充电逻辑耦合到每个输入位线，并且被配置为在时钟周期的第一阶段期间对每个输入位线进行预充电。 输出逻辑可操作地耦合到多个输入位线，以将输出信号设置为第一状态，并且响应于一个或多个输入位线，将输出信号的第一状态保持在至少一个时钟周期 出院
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公开(公告)号：US20130339777A1
公开(公告)日：2013-12-19
申请号：US13994065
申请日：2011-12-30
申请人： Ankush Varma , Jeremy J. Shrall , Krishnakanth Venkata Sistla , Avinash N. Ananthakrishnan , Vivek Garg , Christopher A. Poirier , Martin T. Rowland , Edward R. Stanford
发明人： Ankush Varma , Jeremy J. Shrall , Krishnakanth Venkata Sistla , Avinash N. Ananthakrishnan , Vivek Garg , Christopher A. Poirier , Martin T. Rowland , Edward R. Stanford
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/32 , G06F1/3206 , G06F1/3293 , G06F1/3296 , G06F11/3024 , G06F11/3058
摘要： Dynamic runtime calibration of a processor with respect to a specific voltage regulator that powers the processor or a memory subsystem coupled to the processor can reduce or eliminate the need for guardbands in power management computations. The processor receives a current measurement from the voltage regulator and computes a calibration factor based on the measured value and a stored expected value. The calibration factor can be used in making power management decisions instead of adding the guardband to power readings. A manufacturer or distributor of the processor can compute the stored values with a controlled voltage supply that has a higher precision than typical commercial power supplies used in computing systems. The computed, stored values indicate the expected value, which can be used to determine a calibration factor relative to a voltage regulator of an active system.
摘要翻译： 处理器相对于为处理器供电的特定电压调节器的动态运行时校准，或耦合到处理器的存储器子系统可以减少或消除对电源管理计算中的保护带的需要。 处理器从电压调节器接收电流测量值，并根据测量值和存储的预期值计算校准因子。 校准因子可用于进行电源管理决策，而不是将保护带添加到功率读数。 处理器的制造商或分销商可以使用具有比计算系统中使用的典型商用电源更高精度的受控电压源来计算存储值。 所计算的存储值表示期望值，其可用于确定相对于主动系统的电压调节器的校准因子。
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