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    Method for forming recessed oxide isolation containing deep and shallow trenches
    5.
    发明授权
    Method for forming recessed oxide isolation containing deep and shallow trenches 失效
    用于形成包含深和浅沟槽的凹陷氧化物隔离的方法

    公开(公告)号：US5504033A

    公开(公告)日：1996-04-02

    申请号：US339966

    申请日：1994-11-15

    申请人： George Bajor ,  Anthony L. Rivoli

    发明人： George Bajor ,  Anthony L. Rivoli

    IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/302

    CPC分类号： H01L21/76224 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/76275 ,  H01L21/76283

    摘要： Recessed isolation oxide is deposited in shallow trenches simultaneoulsy with oxide deposition in deep isolation trenches. A single planarization of both trench fillings provides efficient recessed isolation oxide without bird's beak or bird's head problems of LOCOS isolation oxide. Self-aligned trench filling by successive conformal depositions of oxide and polysilicon followed by planarization to remove polysilicon away from the trenches. The the remaining polysilicon may be used as an oxide etch mask to remove all of the oxide except in the trenches.

    摘要翻译： 嵌入的隔离氧化物沉积在浅沟槽中，同时在深隔离沟槽中沉积氧化物。 两个沟槽填充物的单一平面化提供了有效的凹陷隔离氧化物，而没有鸟嘴或LOCOS隔离氧化物的鸟头问题。 通过氧化物和多晶硅的连续共形沉积的自对准沟槽填充，随后进行平面化以从沟槽移除多晶硅。 剩余的多晶硅可以用作氧化物蚀刻掩模以除去除了沟槽中的所有氧化物。

    Method for forming recessed oxide isolation containing deep and shallow trenches
    6.
    发明授权
    Method for forming recessed oxide isolation containing deep and shallow trenches 失效
    用于形成包含深和浅沟槽的凹陷氧化物隔离的方法

    公开(公告)号：US5382541A

    公开(公告)日：1995-01-17

    申请号：US935765

    申请日：1992-08-26

    申请人： George Bajor ,  Anthony L. Rivoli

    发明人： George Bajor ,  Anthony L. Rivoli

    IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/302

    CPC分类号： H01L21/76224 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/76275 ,  H01L21/76283

    摘要： Recessed isolation oxide is deposited in shallow trenches simultaneoulsy with oxide deposition in deep isolation trenches. A single planarization of both trench fillings provides efficient recessed isolation oxide without bird's beak or bird 's head problems of LOCOS isolation oxide. Self-aligned trench filling by successive conformal depositions of oxide and polysilicon followed by planarization to remove polysilicon away from the trenches. The the remaining polysilicon may be used as an oxide etch mask to remove all of the oxide except in the trenches.

    摘要翻译： 嵌入的隔离氧化物沉积在浅沟槽中，同时在深隔离沟槽中沉积氧化物。 两个沟槽填充物的单一平面化提供了有效的凹陷隔离氧化物，而没有鸟喙或LOCOS隔离氧化物的鸟头问题。 通过氧化物和多晶硅的连续共形沉积的自对准沟槽填充，随后进行平面化以从沟槽移除多晶硅。 剩余的多晶硅可以用作氧化物蚀刻掩模以除去除了沟槽中的所有氧化物。

    Bonded wafer
    8.
    发明授权
    Bonded wafer 失效
    粘合晶片

    公开(公告)号：US5744852A

    公开(公告)日：1998-04-28

    申请号：US710694

    申请日：1996-09-19

    申请人： Jack H. Linn ,  George Bajor ,  George V. Rouse

    发明人： Jack H. Linn ,  George Bajor ,  George V. Rouse

    IPC分类号： H01L21/20 ,  H01L29/06

    CPC分类号： H01L21/2007 ,  Y10S148/012 ,  Y10S438/974

    摘要： A bonded wafer with a bond junction having low resistivity due to the low level of oxides at the bond junction. A plasma that removes native oxide layers from wafers is exposed to the wafers. The plasma forms a hydrophobic polymer seal on the wafers, inhibiting subsequent native oxide growth upon exposure to air. The polymer seal on the wafers to be bonded are pressed together and the wafers are annealed to form the bonded wafer in a non-oxidizing ambient. The bond junction formed is primarily silicon to silicon and silicon to carbon bonds.

    摘要翻译： 具有键合结的键合晶片由于在键合结处的氧化物水平低而具有低电阻率。 从晶片去除原生氧化物层的等离子体暴露于晶片。 等离子体在晶片上形成疏水聚合物密封，在暴露于空气中时抑制随后的天然氧化物生长。 将要接合的晶片上的聚合物密封件压在一起，并且将晶片退火以在非氧化环境中形成接合晶片。 所形成的键合键主要是硅与硅和硅与碳键。

    BICMOS process with low temperature coefficient resistor (TCRL)
    10.
    发明授权
    BICMOS process with low temperature coefficient resistor (TCRL) 失效
    BICMOS工艺采用低温系数电阻（TCRL）

    公开(公告)号：US06812108B2

    公开(公告)日：2004-11-02

    申请号：US10393181

    申请日：2003-03-19

    申请人： Donald Hemmenway ,  Jose Delgado ,  John Butler ,  Anthony Rivoli ,  Michael D. Church ,  George V. Rouse ,  Lawrence G. Pearce ,  George Bajor

    发明人： Donald Hemmenway ,  Jose Delgado ,  John Butler ,  Anthony Rivoli ,  Michael D. Church ,  George V. Rouse ,  Lawrence G. Pearce ,  George Bajor

    IPC分类号： H01L2120

    CPC分类号： H01L28/20 ,  H01L21/763 ,  H01L21/8249 ,  H01L27/0635

    摘要： A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient. A process for fabrication of the resistor is used which combines separate spacer oxide depositions, provides buried layers having different diffusion coefficients, incorporates dual dielectric trench sidewalls that double as a polish stop, supplies a spacer structure that controls precisely the emitter-base dimension, and integrates bipolar and CMOS devices with negligible compromise to the features of either type.

    摘要翻译： 低温度系数电阻（TCRL）具有一些未修复的离子注入损伤。 损坏部分会提高电阻，使电阻对工作温度波动较不敏感。 多晶硅薄膜低温系数电阻器和电阻器制造方法克服了现有技术的电阻系数问题，同时消除了BiCMOS制造工艺的步骤，优化了双极设计的权衡，改善了无源器件隔离。 在绝缘层（通常为二氧化硅或氮化硅）上形成电阻电阻器（TCRL）的低温度系数，该层包含具有相对高浓度的一种或多种物质的掺杂剂的多晶硅。 对于注入电阻器而言，使用退火工艺，其比典型的现有技术的注入电阻器的退火工艺短，从而在电阻器中留下一些有意的未退火损坏。 计划的损坏使TCRL具有更高的阻力，而不增加其温度系数。 使用制造电阻器的方法，其组合分开的间隔氧化物沉积，提供具有不同扩散系数的掩埋层，并入双重介质沟槽侧壁作为抛光停止点，提供精确控制发射极基底尺寸的间隔结构，以及 将双极和CMOS器件集成到任何一种类型的特性上都可忽略不计。