公开(公告)号：US06372673B1

公开(公告)日：2002-04-16

申请号：US09781256

申请日：2001-02-13

申请人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

发明人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

IPC分类号： H01L21318

CPC分类号： H01L29/665 ,  H01L21/3185

摘要： Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.

摘要翻译： 通过形成具有基本上没有或显着减少的Si的硅绝缘氮化硅侧壁间隔物来避免金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的桥接，可用于与沉积金属反应， 例如镍。

公开(公告)号：US06387767B1

公开(公告)日：2002-05-14

申请号：US09781448

申请日：2001-02-13

申请人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

发明人： Paul R. Besser ,  Minh Van Ngo ,  Christy Mei-Chu Woo ,  George Jonathan Kluth

IPC分类号： H01L21336

CPC分类号： H01L29/665

摘要： Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and source/drain regions using salicide technology without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming nitrogen-rich silicon nitride sidewall spacers with increased nitrogen, thereby eliminating free Si available to react with the metal subsequently deposited and thus avoiding the formation of metal silicide on the sidewall spacers.

摘要翻译： 使用富含氮的氮化硅侧壁间隔物实现自杀处理，其允许使用硅化物技术在多晶硅栅极电极和源极/漏极区域上形成金属硅化物层，例如NiSi，而不会在栅极上的金属硅化物层之间相互桥接 和源极/漏极区域之间的金属硅化物层。通过形成具有增加的富氮氮化硅侧壁间隔物，避免了金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的结合 氮，从而消除可用于随后沉积的金属的游离Si，从而避免在侧壁间隔物上形成金属硅化物。

公开(公告)号：US06724051B1

公开(公告)日：2004-04-20

申请号：US09679877

申请日：2000-10-05

申请人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  George Jonathan Kluth

发明人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  George Jonathan Kluth

IPC分类号： H01L2976

CPC分类号： H01L29/665 ,  H01L29/4983 ,  Y10S257/90

摘要： A MOSFET semiconductor device includes a substrate, a gate electrode, a gate oxide, first and second sidewall spacers, and nickel silicide layers. The gate oxide is disposed between the gate electrode and the substrate, and the substrate includes source/drain regions. The gate electrode has first and second opposing sidewalls, and the first and second sidewall spacers are respectively disposed adjacent the first and second sidewalls. The first and second sidewall spacers are formed from a low-K spacer material that is substantially non-reactive with nickel, for example, SiHC, hydrogen silsesquioxane and methyl silsesquioxane. The nickel silicide layers are disposed on the source/drain regions and the gate electrode. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： MOSFET半导体器件包括衬底，栅电极，栅极氧化物，第一和第二侧壁间隔物以及镍硅化物层。 栅极氧化物设置在栅极电极和衬底之间，并且衬底包括源极/漏极区域。 栅电极具有第一和第二相对的侧壁，并且第一和第二侧壁间隔件分别设置成与第一和第二侧壁相邻。 第一和第二侧壁间隔物由基本上不与镍反应的低K间隔材料形成，例如SiHC，氢倍半硅氧烷和甲基倍半硅氧烷。 硅化镍层设置在源/漏区和栅电极上。 还公开了制造半导体器件的方法。

公开(公告)号：US06605513B2

公开(公告)日：2003-08-12

申请号：US09729699

申请日：2000-12-06

申请人： Eric N. Paton ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John Clayton Foster ,  Paul L. King ,  George Jonathan Kluth ,  Minh Van Ngo ,  Christy Mei-Chu Woo

发明人： Eric N. Paton ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John Clayton Foster ,  Paul L. King ,  George Jonathan Kluth ,  Minh Van Ngo ,  Christy Mei-Chu Woo

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/4933

摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.

摘要翻译： 自对准硅化物工艺，可以适应低热预算，并在受控反应中形成小尺寸的硅化物区域。 在第一温度处理中，镍金属或镍合金与硅材料反应以形成至少一个高电阻镍硅化物区域。 去除未反应的镍。 然后将电介质层沉积在高电阻镍硅化物区域上。 在第二温度处理中，至少一个高电阻镍硅化物区域和电介质层在规定温度下反应以形成至少一个低电阻硅化物区域并处理介电层。 通过控制硅化物生长的两步法避免区域之间的桥接，并且在第一温度处理之后去除硅化物区域之间的未反应的镍。 将高电阻镍硅化物区域和电介质层的处理方便地组合成单温度处理。

公开(公告)号：US06861350B1

公开(公告)日：2005-03-01

申请号：US10464508

申请日：2003-06-19

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Jinsong Yin ,  James Pan ,  Paul R. Besser

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Jinsong Yin ,  James Pan ,  Paul R. Besser

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H10L21/4763 ,  H10L21/44

CPC分类号： H01L29/66606 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545

摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.

摘要翻译： 微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。 实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中 的富硅钽硅氮化物。 在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。 实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

公开(公告)号：US06548403B1

公开(公告)日：2003-04-15

申请号：US09679871

申请日：2000-10-05

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L29/6659

摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by forming a relatively thick silicon oxide liner on the side surfaces of the gate electrode and adjacent surface of the semiconductor substrate before forming the silicon nitride sidewall spacers thereon. Embodiments include forming a silicon dioxide liner at a thickness of about 200 Å to about 600 Å prior to forming the silicon nitride sidewall spacers thereon.

摘要翻译： 在形成氮化硅侧壁之前，通过在栅电极的侧表面和半导体衬底的相邻表面上形成相对较厚的氧化硅衬垫来防止在栅电极上的硅化镍层与氮化硅侧壁间隔物之间​​的源极/漏极区之间的桥接 垫片。 在形成氮化硅侧壁间隔物之前，实施例包括在大约至大约600埃的厚度形成二氧化硅衬垫。

公开(公告)号：US06432817B1

公开(公告)日：2002-08-13

申请号：US09731024

申请日：2000-12-07

申请人： Jacques J. Bertrand ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  George Kluth

发明人： Jacques J. Bertrand ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  George Kluth

IPC分类号： H01L214763

CPC分类号： H01L29/4941 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： Nickel silicidation of a gate electrode is controlled using a tungsten silicide barrier layer. Embodiments include forming a gate electrode structure comprising a lower polycrystalline silicon layer, a layer of tungsten silicide thereon and an upper polycrystalline silicon layer on the tungsten silicide layer, depositing a layer of nickel and silicidizing, whereby the upper polycrystalline silicon layer is converted to nickel silicide and the tungsten silicide barrier layer prevents nickel from reacting with the lower polycrystalline silicon layer.

摘要翻译： 使用硅化钨阻挡层来控制栅电极的镍硅化。 实施例包括在硅化钨层上形成包括下多晶硅层，硅化钨层和上多晶硅层的栅电极结构，沉积镍层和硅化层，由此将上多晶硅层转变为镍 硅化物和硅化钨阻挡层防止镍与下部多晶硅层反应。

公开(公告)号：US06661067B1

公开(公告)日：2003-12-09

申请号：US10260514

申请日：2002-10-01

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

IPC分类号： H01L2994

CPC分类号： H01L29/665 ,  H01L21/3115 ,  Y10S257/90

摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

摘要翻译： 通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面来形成具有减少的游离硅的表面区域，防止栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

公开(公告)号：US06657304B1

公开(公告)日：2003-12-02

申请号：US10165510

申请日：2002-06-06

申请人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

发明人： Christy Mei-Chu Woo ,  Minh Van Ngo ,  John E. Sanchez, Jr. ,  Steven C. Avanzino

IPC分类号： H01L2352

CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76871 ,  H01L21/76876 ,  H01L2221/1089

摘要： A manufacturing method, and an integrated circuit resulting therefrom, has a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.

摘要翻译： 一种制造方法和由此产生的集成电路在其上具有基板和半导体器件。 衬底上的停止层具有形成在其上的第一电介质层，其上形成有第一共形势垒的开口。 在开口中形成第一共形阻挡衬里，加工和处理以改善粘附性。 侧壁上的第一共形阻挡衬里的部分作为导体芯材料扩散到第一介电层的障碍。 导体材料形成在第一共形阻挡衬里和第一止挡层的垂直部分上的开口中。

公开(公告)号：US06593237B1

公开(公告)日：2003-07-15

申请号：US10179047

申请日：2002-06-24

申请人： Minh Van Ngo ,  Christy Mei-Chu Woo

发明人： Minh Van Ngo ,  Christy Mei-Chu Woo

IPC分类号： H01L2144

CPC分类号： H01L23/5329 ,  H01L21/76807 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening and a conductor core filling the channel opening. A via stop layer is formed over the channel dielectric layer to have a hydrogen concentration below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core, filling the second channel opening and the via opening, is connected to the semiconductor device.

摘要翻译： 提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。 器件电介质层上的沟道电介质层具有通道开口和填充沟道开口的导体芯。 在通道电介质层上形成通孔停止层，使氢浓度低于15原子％，并且在通孔停止层上方形成通孔电介质层，并具有通孔。 通孔电介质层上的第二通道介电层具有第二通道开口。 填充第二通道开口和通孔开口的第二导体芯连接到半导体器件。