公开(公告)号：US06756671B2

公开(公告)日：2004-06-29

申请号：US10190274

申请日：2002-07-05

Applicant: Chu-Sheng Lee ,  Chu-We Hu ,  Yu-Lung Yeh ,  Sheng-Hung Chou

Inventor： Chu-Sheng Lee ,  Chu-We Hu ,  Yu-Lung Yeh ,  Sheng-Hung Chou

IPC: H01L2348

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L23/5226 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A method of making a microelectronic device providing a base substrate having a bond pad, a first passivation layer overlying the base substrate and a portion of the bond pad, and a second passivation layer overlying the first passivation layer; forming a first sacrificial layer over the second passivation layer, wherein the first sacrificial layer includes an opening therethrough; etching the exposed portion of the second passivation layer to provide a recess therein; trimming a portion of the first sacrificial layer to enlarge the opening; etching the exposed portion of the second passivation layer to provide an enlarged recess and a first riser, a second tread, a second riser and a second tread; removing the first sacrificial layer; depositing a redistribution layer into the enlarged recess in the second passivation layer and over the first riser, first tread, second riser, and second tread.

Abstract translation: 一种制造提供具有接合焊盘的基底基板的微电子器件的方法，覆盖基底衬底的第一钝化层和接合焊盘的一部分以及覆盖第一钝化层的第二钝化层; 在所述第二钝化层上形成第一牺牲层，其中所述第一牺牲层包括穿过其的开口; 蚀刻第二钝化层的暴露部分以在其中提供凹陷; 修剪第一牺牲层的一部分以扩大开口; 蚀刻第二钝化层的暴露部分以提供扩大的凹部，第一提升管，第二胎面，第二提升管和第二胎面; 去除第一牺牲层; 将再分布层沉积到第二钝化层中的扩大凹部中，并且在第一提升管，第一胎面，第二提升管和第二胎面之上。

公开(公告)号：US08932937B2

公开(公告)日：2015-01-13

申请号：US10151442

申请日：2002-05-20

Applicant: Chu-Sheng Lee ,  Hsin-Chi Chen ,  Chu-Wei Hu

Inventor： Chu-Sheng Lee ,  Hsin-Chi Chen ,  Chu-Wei Hu

IPC: H01L21/76

CPC classification number: H01L21/76229

Abstract: Defining an oxide define region (ODR) without using a photomask is disclosed. Pad oxide and a stop layer are deposited over peaks of a substrate of a semiconductor wafer. The pad oxide may be silicon oxide, whereas the stop layer may be silicon nitride. Oxide, such as high-density plasma (HDP) oxide, is deposited over the pad oxide, the stop layer, and valleys of the substrate of the semiconductor wafer. A hard mask, such as silicon nitride, is deposited over the oxide, and photoresist is deposited over the hard mask. The photoresist is etched back until peaks of the hard mask are exposed. The peaks of the hard mask and the oxide underneath are etched through to the stop layer, and the photoresist is removed. Chemical-mechanical planarization (CMP) can then be performed on the hard mask that remains and the oxide underneath through to the stop layer, and the stop layer removed.

公开(公告)号：US20070045871A1

公开(公告)日：2007-03-01

申请号：US11209805

申请日：2005-08-24

Applicant: Chu-Sheng Lee

Inventor： Chu-Sheng Lee

IPC: H01L23/48

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A pad open structure, after an insulation layer is installed at the up of the pad, the insulation layer forms plural pad opens by lithography. The insulation layer is exposed to the surface of the pad by the pad opens. The gold bump forms the upper part of the insulation layer, which forms an electric connection through the pad opens to the pad. By way of this, when the gold bump is formed at the surface of the pad opens and the surrounding insulation layer, reducing the affection produced by a single pad open that hollows the surface of the gold bump such that the gold bump has an extra flat surface.

Abstract translation: 衬垫开放结构，在绝缘层安装在衬垫的上方之后，绝缘层通过光刻形成多个衬垫开口。 绝缘层通过焊盘打开而暴露于焊盘的表面。 金凸块形成绝缘层的上部，其通过焊盘形成电连接，通向焊盘。 通过这种方式，当在焊盘的表面上形成金凸块并且围绕绝缘层时，减少由单个焊盘打开产生的影响，从而使金凸块的表面凹陷，使得金凸块具有额外的平坦 表面。

公开(公告)号：US20060132995A1

公开(公告)日：2006-06-22

申请号：US11013351

申请日：2004-12-17

Applicant: Chu-Sheng Lee

Inventor： Chu-Sheng Lee

IPC: H02H9/00

CPC classification number: H01L27/0251 ,  H01L27/0292

Abstract: The present invention relates to a method of whole-chip electrostatic discharge protection, wherein the chip has a first metallic layer and a second metallic layer, and each surrounds the chip along the trail keeping an appropriate spacing away from the perimeter of the chip separately, and in contrast to the first type semiconductor substrate, a second type semiconductor well is formed below the first metallic layer. The second type semiconductor well, which surrounds the chip along the trail keeping an appropriate spacing away from the perimeter of the chip, can function as a large capacitor to store the discharged electricity. Thereby, the electrostatic discharge protection of the whole chip can be promoted with no increasing chip area needed and without changing the original design and manufacture process of IC.

Abstract translation: 本发明涉及一种全片式静电放电保护方法，其中芯片具有第一金属层和第二金属层，并且各自围绕芯片围绕芯片分开保持与芯片的周边相适应的间隔， 并且与第一类型半导体衬底相反，在第一金属层的下面形成第二类型的半导体阱。 围绕芯片围绕芯片的第二类型的半导体阱保持与芯片的周边相适应的间隔，可以用作存储放电的大电容器。 因此，不需要增加芯片面积就可以促进整个芯片的静电放电保护，而不改变IC的原始设计和制造过程。

公开(公告)号：US06852472B2

公开(公告)日：2005-02-08

申请号：US10272655

申请日：2002-10-17

Applicant: Chu-Sheng Lee ,  Tou-Yu Chen

Inventor： Chu-Sheng Lee ,  Tou-Yu Chen

IPC: B44C1/22 ,  C03C25/68 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32134 ,  H01L21/32139 ,  H01L21/76838

Abstract: The removal of defect particles that may be created during polysilicon hard mask etching, and that are embedded within the polysilicon layer, is disclosed. Oxide is first grown in the polysilicon layer exposed through the patterned hard mask layer, so that the defect particle becomes embedded within the oxide. Oxide growth may be accomplished by rapid thermal oxidation (RTO). The oxide is then exposed to an acidic solution, such as hydrofluoric (HF) acid, to remove the oxide and the embedded defect particle embedded therein.

Abstract translation: 公开了可以在多晶硅硬掩模蚀刻期间产生并且嵌入在多晶硅层内的缺陷颗粒的去除。 氧化物首先在通过图案化的硬掩模层暴露的多晶硅层中生长，使得缺陷颗粒嵌入氧化物内。 氧化物生长可以通过快速热氧化（RTO）来实现。 然后将氧化物暴露于诸如氢氟酸（HF）酸的酸性溶液中以除去嵌入其中的氧化物和嵌入的缺陷颗粒。