利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

37 条记录 (耗时 0.025 秒)

    Semiconductor Device and Fabrication Method Thereof
    1.
    发明申请
    Semiconductor Device and Fabrication Method Thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US20140021517A1

    公开(公告)日：2014-01-23

    申请号：US13551107

    申请日：2012-07-17

    申请人： Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

    发明人： Chun-Fai Cheng ,  Han-Ting Tsai ,  An-Shen Chang ,  Hui-Min Lin

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

    摘要： A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.

    摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 在衬底中形成隔离结构，并且在隔离结构的顶部形成栅叠层。 邻接栅叠层的侧壁并且延伸超出隔离结构的边缘的间隔件。 所公开的方法提供了通过使用间隔物来保护隔离结构的改进方法。 间隔件可以防止隔离结构被化学物质损坏，从而增强接触着陆和提升设备性能。

    Method for fabricating a gate structure
    4.
    发明授权
    Method for fabricating a gate structure 有权
    栅极结构的制造方法

    公开(公告)号：US08535998B2

    公开(公告)日：2013-09-17

    申请号：US12720075

    申请日：2010-03-09

    申请人： Fung Ka Hing ,  Haiting Wang ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

    发明人： Fung Ka Hing ,  Haiting Wang ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Wei-Yuan Lu ,  Hsien-Ching Lo ,  Kuan-Chung Chen

    IPC分类号： H01L21/338

    CPC分类号： H01L29/7833 ,  H01L21/76834 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7836

    摘要： The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.

    摘要翻译： 本公开公开了一种用于制造栅极结构的示例性方法，其包括在衬底上沉积和图案化虚拟氧化物层和伪栅极电极层; 围绕所述虚拟氧化物层和所述伪栅极电极层，具有牺牲层; 用含氮介电层围绕牺牲层; 用层间介质层包围含氮介电层; 去除所述伪栅电极层; 去除虚拟氧化物层; 去除所述牺牲层以在所述含氮介电层中形成开口; 并沉积栅极电介质; 并沉积栅电极。

    Self-aligned two-step STI formation through dummy poly removal
    6.
    发明授权
    Self-aligned two-step STI formation through dummy poly removal 有权
    自对准两步STI形成通过虚拟多重去除

    公开(公告)号：US08502316B2

    公开(公告)日：2013-08-06

    申请号：US12704367

    申请日：2010-02-11

    申请人： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

    发明人： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

    IPC分类号： H01L29/72

    CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    摘要： An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.

    摘要翻译： 集成电路结构包括包括有源区的半导体衬底。 第一浅沟槽隔离（STI）区域邻接有源区域的第一侧。 MOS器件的栅电极在有源区和第一STI区之上。 MOS器件的源极/漏极应力区域包括半导体衬底中的与栅电极相邻的部分。 在半导体衬底中形成沟槽，并与有源区域的第二面相邻。 沟槽的底部不低于源极/漏极区域的底部。 层间电介质（ILD）从栅极电极延伸到沟槽内部，其中沟槽中的ILD的一部分形成第二STI区域。 第二STI区域和源极/漏极应力区域彼此分离并邻接半导体衬底的一部分。

    MULTI-STRAINED SOURCE/DRAIN STRUCTURES
    7.
    发明申请
    MULTI-STRAINED SOURCE/DRAIN STRUCTURES 有权
    多应变源/排水结构

    公开(公告)号：US20110291201A1

    公开(公告)日：2011-12-01

    申请号：US12787972

    申请日：2010-05-26

    申请人： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

    发明人： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

    IPC分类号： H01L27/088 ,  H01L21/8234

    CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

    摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

    摘要翻译： 本发明提供一种半导体器件。 半导体器件包括硅衬底。 半导体器件包括设置在衬底中的第一和第二区域。 第一和第二区域具有硅化合物材料。 半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源/漏结构。 半导体器件包括设置在衬底上的第一栅极。 第一个门第一个靠近第一个地区。 半导体器件包括设置在衬底上的第二栅极。 第二个门第二个靠近第二个区域。 第二接近度不同于第一接近度。 第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

    Multi-strained source/drain structures
    8.
    发明授权
    Multi-strained source/drain structures 有权
    多应变源/漏结构

    公开(公告)号：US08405160B2

    公开(公告)日：2013-03-26

    申请号：US12787972

    申请日：2010-05-26

    申请人： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

    发明人： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

    IPC分类号： H01L27/088 ,  H01L21/8238

    CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

    摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

    摘要翻译： 本发明提供一种半导体器件。 半导体器件包括硅衬底。 半导体器件包括设置在衬底中的第一和第二区域。 第一和第二区域具有硅化合物材料。 半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源极/漏极结构。 半导体器件包括设置在衬底上的第一栅极。 第一个门第一个靠近第一个地区。 半导体器件包括设置在衬底上的第二栅极。 第二个门第二个靠近第二个区域。 第二接近度与第一接近度不同。 第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

    Self-Aligned Two-Step STI Formation Through Dummy Poly Removal
    10.
    发明申请
    Self-Aligned Two-Step STI Formation Through Dummy Poly Removal 有权
    通过透明多余去除自对准两步STI形成

    公开(公告)号：US20110193167A1

    公开(公告)日：2011-08-11

    申请号：US12704367

    申请日：2010-02-11

    申请人： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

    发明人： Ka-Hing Fung ,  Han-Ting Tsai ,  Chun-Fai Cheng ,  Haiting Wang ,  Wei-Yuan Lu ,  Hsien-Ching Lo

    IPC分类号： H01L27/12 ,  H01L27/105

    CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    摘要： An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate.

    摘要翻译： 集成电路结构包括包括有源区的半导体衬底。 第一浅沟槽隔离（STI）区域邻接有源区域的第一侧。 MOS器件的栅电极在有源区和第一STI区之上。 MOS器件的源极/漏极应力区域包括半导体衬底中的与栅电极相邻的部分。 在半导体衬底中形成沟槽，并与有源区域的第二面相邻。 沟槽的底部不低于源极/漏极区域的底部。 层间电介质（ILD）从栅极电极延伸到沟槽内部，其中沟槽中的ILD的一部分形成第二STI区域。 第二STI区域和源极/漏极应力区域彼此分离并邻接半导体衬底的一部分。