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    Manufacturing method of semiconductor device
    1.
    发明授权
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US07915127B2

    公开(公告)日：2011-03-29

    申请号：US12509623

    申请日：2009-07-27

    申请人： Chun-Hsien Lin ,  Chao-Ching Hsieh

    发明人： Chun-Hsien Lin ,  Chao-Ching Hsieh

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833

    摘要： A method of forming a semiconductor device is described. First, a substrate is provided. Thereafter, a gate structure including, from bottom to top, a high-k layer, a work function metal layer, a wetting layer, a polysilicon layer and a mask layer is formed on the substrate. Afterwards, a spacer is formed on the sidewall of the gate structure. Source/drain regions are then formed in the substrate beside the gate structure. Further, an interlayer dielectric layer is formed over the substrate. Thereafter, a portion of the interlayer dielectric layer is removed to expose the surface of the mask layer. Afterwards, the mask layer and the polysilicon layer are sequentially removed to expose the surface of the wetting layer. A selective chemical vapor deposition process is then performed, so as to bottom-up deposit a metal layer from the surface of the wetting layer.

    摘要翻译： 描述形成半导体器件的方法。 首先，提供基板。 此后，在基板上形成从底部到顶部包括高k层，功函数金属层，润湿层，多晶硅层和掩模层的栅极结构。 之后，在栅极结构的侧壁上形成间隔物。 然后在栅极结构旁边的衬底中形成源/漏区。 此外，在衬底上形成层间电介质层。 此后，去除部分层间电介质层以暴露掩模层的表面。 然后，依次去除掩模层和多晶硅层以露出润湿层的表面。 然后进行选择性化学气相沉积工艺，以便从底层向下从润湿层的表面沉积金属层。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08405143B2

    公开(公告)日：2013-03-26

    申请号：US13031910

    申请日：2011-02-22

    申请人： Chun-Hsien Lin ,  Chao-Ching Hsieh

    发明人： Chun-Hsien Lin ,  Chao-Ching Hsieh

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7843

    摘要： A semiconductor device including a substrate, a gate structure, a spacer and source/drain regions is provided. The gate structure is on the substrate, wherein the gate structure includes, from bottom to top, a high-k layer, a work function metal layer, a wetting layer and a metal layer. The spacer is on a sidewall of the gate structure. The source/drain regions are in the substrate beside the gate structure.

    摘要翻译： 提供了包括衬底，栅极结构，间隔物和源极/漏极区域的半导体器件。 栅极结构在衬底上，其中栅极结构从底部到顶部包括高k层，功函数金属层，润湿层和金属层。 间隔物位于栅极结构的侧壁上。 源极/漏极区域位于栅极结构旁边的衬底中。

    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    3.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
    半导体器件的制造方法

    公开(公告)号：US20110020994A1

    公开(公告)日：2011-01-27

    申请号：US12509623

    申请日：2009-07-27

    申请人： Chun-Hsien Lin ,  Chao-Ching Hsieh

    发明人： Chun-Hsien Lin ,  Chao-Ching Hsieh

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833

    摘要： A method of forming a semiconductor device is described. First, a substrate is provided. Thereafter, a gate structure including, from bottom to top, a high-k layer, a work function metal layer, a wetting layer, a polysilicon layer and a mask layer is formed on the substrate. Afterwards, a spacer is formed on the sidewall of the gate structure. Source/drain regions are then formed in the substrate beside the gate structure. Further, an interlayer dielectric layer is formed over the substrate. Thereafter, a portion of the interlayer dielectric layer is removed to expose the surface of the mask layer. Afterwards, the mask layer and the polysilicon layer are sequentially removed to expose the surface of the wetting layer. A selective chemical vapor deposition process is then performed, so as to bottom-up deposit a metal layer from the surface of the wetting layer.

    摘要翻译： 描述形成半导体器件的方法。 首先，提供基板。 此后，在基板上形成从底部到顶部包括高k层，功函数金属层，润湿层，多晶硅层和掩模层的栅极结构。 之后，在栅极结构的侧壁上形成间隔物。 然后在栅极结构旁边的衬底中形成源/漏区。 此外，在衬底上形成层间电介质层。 此后，去除部分层间电介质层以暴露掩模层的表面。 然后，依次去除掩模层和多晶硅层以露出润湿层的表面。 然后进行选择性化学气相沉积工艺，以便从底层向下从润湿层的表面沉积金属层。

    Device performance parmeter tuning method and system
    5.
    发明授权
    Device performance parmeter tuning method and system 有权
    设备性能参数调节方法和系统

    公开(公告)号：US08452439B2

    公开(公告)日：2013-05-28

    申请号：US13048282

    申请日：2011-03-15

    申请人： Sunny Wu ,  Chun-Hsien Lin ,  Kun-Ming Chen ,  Dung-Yian Hsieh ,  Hui-Ru Lin ,  Jo Fei Wang ,  Jong-I Mou ,  I-Ching Chu

    发明人： Sunny Wu ,  Chun-Hsien Lin ,  Kun-Ming Chen ,  Dung-Yian Hsieh ,  Hui-Ru Lin ,  Jo Fei Wang ,  Jong-I Mou ,  I-Ching Chu

    IPC分类号： G06F19/00 ,  G01N37/00 ,  G06F11/30 ,  G21C17/00

    CPC分类号： H01L22/20 ,  G01R31/2894 ,  H01L22/14

    摘要： A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure. The at least one new process parameter value is to be used to process at least one additional wafer.

    摘要翻译： 一种方法包括基于在晶片电测试期间识别的多个故障来计算多个故障仓中的每一个的相应回归模型。 每个回归模型输出作为多个设备性能变量的函数的晶片产量测量。 对于每个故障仓，确定晶片产量测量对多个器件性能变量中的每一个的灵敏度，并且相对于晶片产量测量的灵敏度对器件性能变量进行排序。 选择具有最高排名并且彼此具有小于阈值相关性的设备性能变量的子集。 组合对应于所选择的设备性能变量子集之一的每个故障仓的晶片产量测量，以提供组合晶片产量测量。 选择至少一个新的过程参数值，以基于组合的晶片产量测量来实现一个器件性能变量的变化。 至少一个新的过程参数值将用于处理至少一个附加晶片。

    Supporting device with wheels
    9.
    发明授权
    Supporting device with wheels 有权
    带轮的支撑装置

    公开(公告)号：US08292309B2

    公开(公告)日：2012-10-23

    申请号：US12701688

    申请日：2010-02-08

    申请人： Chen-Lu Fan ,  Chih-Kun Shih ,  Chun-Hsien Lin

    发明人： Chen-Lu Fan ,  Chih-Kun Shih ,  Chun-Hsien Lin

    IPC分类号： B62D33/02

    CPC分类号： B60B37/10

    摘要： A supporting device includes a tray, a plurality of wheel assemblies, a handle, and a handgrip. The tray is configured for supporting a payload. The wheel assemblies are secured to the tray, and each wheel assembly includes a wheel. Each wheel is capable of rotating about a first axis. The wheel assemblies are rotatable between a first position and a second position, and a distance between each wheel and the tray in the first position is smaller than a distance between each wheel and the tray in the second position. The handle is attached to the tray and configured to urge the wheel assemblies to rotate from the first position to the second position. The handgrip is attached to the tray and configured to urge the wheel assemblies to rotate from the second position to the first position.

    摘要翻译： 支撑装置包括托盘，多个轮组件，手柄和手柄。 托盘配置为支持有效载荷。 车轮组件被固定到托盘，并且每个车轮组件包括车轮。 每个车轮能够围绕第一轴线旋转。 车轮组件可在第一位置和第二位置之间转动，并且在第一位置的每个车轮和托盘之间的距离小于在第二位置的每个车轮和托盘之间的距离。 手柄连接到托盘并构造成推动车轮组件从第一位置旋转到第二位置。 手柄附接到托盘并且构造成推动车轮组件从第二位置旋转到第一位置。

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20120034747A1

    公开(公告)日：2012-02-09

    申请号：US13277384

    申请日：2011-10-20

    申请人： Chun-Hsien Lin

    发明人： Chun-Hsien Lin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

    摘要： A method for fabricating a semiconductor device is described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively.

    摘要翻译： 对半导体装置的制造方法进行说明。 在基板上形成多晶硅层。 多晶硅层掺杂有N型掺杂剂。 然后去除多晶硅层的一部分以形成多个虚拟图案。 每个虚拟图案具有布置在顶部和底部之间的顶部，底部和颈部，其中颈部的宽度比顶部的宽度窄。 在基板上形成电介质层以覆盖设置在相邻虚设图案之间的基板，并且暴露每个虚设图案的顶部。 此后，去除虚拟图案以在电介质层中形成多个沟槽。 在沟槽中分别形成多个栅极结构。