公开(公告)号：US08778717B2

公开(公告)日：2014-07-15

申请号：US12726215

申请日：2010-03-17

申请人： Ru-Shang Hsiao ,  Chung-Te Lin ,  Nai-Wen Cheng ,  Yin-Kai Liao ,  Wei Chuang Wu

发明人： Ru-Shang Hsiao ,  Chung-Te Lin ,  Nai-Wen Cheng ,  Yin-Kai Liao ,  Wei Chuang Wu

IPC分类号： H01L21/00

CPC分类号： H01L21/76213 ,  H01L21/26513 ,  H01L21/26533 ,  H01L31/103 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.

摘要翻译： 形成集成电路结构的方法包括提供硅衬底，并将p型杂质注入硅衬底中以形成p型区域。 在注入步骤之后，进行退火以形成氧化硅区域，其中一部分p型区域转换为氧化硅区域。

公开(公告)号：US08158474B2

公开(公告)日：2012-04-17

申请号：US12873889

申请日：2010-09-01

申请人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

发明人： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

IPC分类号： H01L21/0243 ,  H01L23/76

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

摘要翻译： 提供具有局部应力源的诸如PMOS晶体管的半导体器件。 凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。 这些凹部填充有应力诱导层。 去除虚拟凹槽并形成轻掺杂的排水沟。 此后，形成新的间隔物并且应力诱导层凹陷。 可以执行一个或多个附加植入物以完成源极/漏极区域。 在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。 也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

公开(公告)号：US08051392B2

公开(公告)日：2011-11-01

申请号：US12212088

申请日：2008-09-17

申请人： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

发明人： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

IPC分类号： G06F17/50 ,  G06F7/66 ,  G06K9/00 ,  H01L21/66

摘要： A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.

公开(公告)号：US20080272410A1

公开(公告)日：2008-11-06

申请号：US11743519

申请日：2007-05-02

申请人： Chung-Te Lin

发明人： Chung-Te Lin

IPC分类号： H01L29/76

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76831 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A metal-oxide-semiconductor field-effect transistor (MOSFET) having self-aligned spacer contacts is provided. In accordance with embodiments of the present invention, a transistor, having a gate electrode and source/drain regions formed on opposing sides of the gate electrode, is covered with a first dielectric layer. A first contact opening is formed in the first dielectric layer to expose at least a portion of one of the source/drain regions. A second dielectric layer is formed over the first dielectric layer. Thereafter, an inter-layer dielectric layer is formed over the second dielectric layer and a second contact opening is formed through the inter-layer dielectric layer. In an embodiment, an etch-back process may be performed on the second dielectric layer prior to forming the inter-layer dielectric layer.

摘要翻译： 提供了具有自对准间隔触点的金属氧化物半导体场效应晶体管（MOSFET）。 根据本发明的实施例，具有形成在栅电极的相对侧上的栅电极和源极/漏极区的晶体管被​​第一介电层覆盖。 在第一电介质层中形成第一接触开口以暴露源/漏区之一的至少一部分。 在第一电介质层上形成第二电介质层。 此后，在第二电介质层上形成层间电介质层，通过层间电介质层形成第二接触开口。 在一个实施例中，可以在形成层间电介质层之前在第二电介质层上执行回蚀工艺。

公开(公告)号：US20060292770A1

公开(公告)日：2006-12-28

申请号：US11290914

申请日：2005-11-30

申请人： I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

发明人： I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

IPC分类号： H01L21/337 ,  H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

摘要： Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the direction, which is the direction where hole mobility is maximum for a {110} substrate.

摘要翻译： 提供了使用双重SOI衬底的具有混合晶体取向的CMOS器件的方法和结构。 根据优选实施例，制造顺序包括在形成浅沟槽隔离区的步骤之后形成SOI硅外延层的步骤。 优选的顺序允许混合SOI CMOS制造，而不会遇到在外延后形成STI区域引起的问题。 优选的器件包括{100}晶体取向的NFET和{110}晶体取向的PFET。 可以沿着<100>方向取向NMOS沟道，这是{100}衬底的最大电子迁移率的方向。 可以沿着<110>方向取向PMOS沟道，这是{110}衬底的空穴迁移率最大的方向。

公开(公告)号：US06287926B1

公开(公告)日：2001-09-11

申请号：US09253297

申请日：1999-02-19

申请人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

发明人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

摘要翻译： 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US6063695A

公开(公告)日：2000-05-16

申请号：US192451

申请日：1998-11-16

申请人： Chung-Te Lin ,  Chin-Hsiung Ho ,  Hsueh-Liang Chiu ,  So-Wein Kuo

发明人： Chung-Te Lin ,  Chin-Hsiung Ho ,  Hsueh-Liang Chiu ,  So-Wein Kuo

IPC分类号： H01L21/304 ,  H01L23/544 ,  H01L21/301

CPC分类号： H01L23/544 ,  H01L21/3043 ,  H01L2223/54433 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10S148/028 ,  Y10S438/94

摘要： A process for the formation of deep clear laser marks on silicon wafers is described. Tall ridges of material which is erupted from the wafer surface during the deep laser penetration form adjacent to the marks. These ridges are of the order of 3 to 15 microns in height and must be removed prior to subsequent wafer processing to avoid fragmentation causing scratches and particulate contamination. The process of the invention deposits a non-conformal layer of photoresist or other flowable material on the wafer. The peaks of the ridges protrude above the surface of the conformal layer be a significant amount and are then etched away using an aqueous silicon etch. The non-conformal layer protects the wafer surface from the silicon etch so that only the ridges are removed. After the ridges are etched, the non-conformal layer is removed leaving residual ridges of a height less than or equal to the thickness of the conformal layer.

摘要翻译： 描述了在硅晶片上形成深度清晰的激光标记的工艺。 在深度激光穿透期间从晶片表面喷出的与标记相邻的材料的高隆起。 这些脊的高度为3至15微米的数量级，并且必须在随后的晶片加工之前被去除，以避免碎片引起划痕和颗粒污染。 本发明的方法在晶片上沉积光致抗蚀剂或其它可流动材料的非共形层。 突起在保形层表面之上的脊的峰值是相当大的量，然后使用含水硅蚀刻蚀刻掉。 非保形层保护晶片表面免受硅蚀刻，从而仅去除脊。 在蚀刻脊之后，去除非共形层，留下高度小于或等于共形层厚度的残留脊。

公开(公告)号：US07611937B2

公开(公告)日：2009-11-03

申请号：US11281029

申请日：2005-11-17

申请人： Chung-Te Lin ,  I-Lu Wu ,  Mariam Sadaka

发明人： Chung-Te Lin ,  I-Lu Wu ,  Mariam Sadaka

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/78

摘要： A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively, and wherein the substrate comprises a first region and a second region. An isolation structure is formed in the second region extending to the first semiconductor layer. A trench is then formed in the isolation structure, exposing the first semiconductor layer. A semiconductor material is epitaxially grown in the trench. The method further includes forming a MOSFET of a first type on the second semiconductor layer and a MOSFET of an opposite type than the first type on the epitaxially grown semiconductor material.

摘要翻译： 提供一种形成具有混合晶体取向的半导体结构并形成在半导体结构上具有改进性能的MOSFET的方法。 该方法包括在第一半导体层上提供包括掩埋氧化物（BOX）的衬底和BOX上的第二半导体层，其中第一和第二半导体层分别具有第一和第二晶体取向，并且其中衬底 包括第一区域和第二区域。 在延伸到第一半导体层的第二区域中形成隔离结构。 然后在隔离结构中形成沟槽，暴露第一半导体层。 半导体材料在沟槽中外延生长。 该方法还包括在外延生长的半导体材料上在第二半导体层上形成第一类型的MOSFET和与第一类型相反的MOSFET。

公开(公告)号：US20060292834A1

公开(公告)日：2006-12-28

申请号：US11281029

申请日：2005-11-17

申请人： Chung-Te Lin ,  I-Lu Wu ,  Mariam Sadaka

发明人： Chung-Te Lin ,  I-Lu Wu ,  Mariam Sadaka

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/78

摘要： A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively, and wherein the substrate comprises a first region and a second region. An isolation structure is formed in the second region extending to the first semiconductor layer. A trench is then formed in the isolation structure, exposing the first semiconductor layer. A semiconductor material is epitaxially grown in the trench. The method further includes forming a MOSFET of a first type on the second semiconductor layer and a MOSFET of an opposite type than the first type on the epitaxially grown semiconductor material.

公开(公告)号：US06583017B2

公开(公告)日：2003-06-24

申请号：US09927072

申请日：2001-08-10

申请人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

发明人： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

摘要翻译： 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。