公开(公告)号：US06838354B2

公开(公告)日：2005-01-04

申请号：US10327403

申请日：2002-12-20

申请人： Cindy K. Goldberg ,  Stanley Michael Filipiak ,  John C. Flake ,  Yeong-Jyh T. Lii ,  Bradley P. Smith ,  Yuri E. Solomentsev ,  Terry G. Sparks ,  Kirk J. Strozewski ,  Kathleen C. Yu

发明人： Cindy K. Goldberg ,  Stanley Michael Filipiak ,  John C. Flake ,  Yeong-Jyh T. Lii ,  Bradley P. Smith ,  Yuri E. Solomentsev ,  Terry G. Sparks ,  Kirk J. Strozewski ,  Kathleen C. Yu

IPC分类号： H01L21/288 ,  H01L21/768 ,  H01L21/76

CPC分类号： H01L21/76844 ,  H01L21/288 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76874

摘要： Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

公开(公告)号：US06764919B2

公开(公告)日：2004-07-20

申请号：US10327498

申请日：2002-12-20

申请人： Kathleen C. Yu ,  Edward O. Travis ,  Bradley P. Smith

发明人： Kathleen C. Yu ,  Edward O. Travis ,  Bradley P. Smith

IPC分类号： H01L2176

CPC分类号： H01L21/76852 ,  H01L21/7682 ,  H01L21/76874 ,  H01L23/522 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： Dummy features (64, 65a, 65b, 48a, 48b) are formed within an interlevel dielectric layer (36). A non-gap filling dielectric layer (72) is formed over the dummy features (64, 65a, 65b, 48a, 48b) to form voids (74) between dummy features (64, 65a, 65b, 48a, 48b) or between a dummy feature (48a) and a current carrying region (44). The dummy features (64, 65a, 65b, 48a, 48b) can be conductive (48a, 48b) and therefore, formed when forming the current carrying region (44). In another embodiment, the dummy features (64, 65a, 65b, 48a, 48b) are insulating (64, 65a, 65b) and are formed after forming the current carrying region (44). In yet another embodiment, both conductive and insulating dummy features (64, 65a, 65b, 48a, 48b) are formed. In a preferred embodiment, the voids (74) are air gaps, which are a low dielectric constant material.

摘要翻译： 在层间电介质层（36）内形成虚拟特征（64,65a，65b，48a，48b）。 在虚拟特征（64,65a，65b，48a，48b）上形成无间隙填充介电层（72），以在虚拟特征（64,65a，65b，48a，48b）之间或之间形成空隙（74） 虚拟特征（48a）和载流区（44）。 虚拟特征（64,65a，65b，48a，48b）可以是导电的（48a，48b），因此在形成载流区域（44）时形成。 在另一个实施例中，虚拟特征（64,65a，65b，48a，48b）是绝缘的（64,65a，65b），并且在形成载流区域（44）之后形成。 在又一个实施例中，形成导电和绝缘虚拟特征（64,65a，65b，48a，48b）。 在优选实施例中，空隙（74）是作为低介电常数材料的气隙。

公开(公告)号：US08426263B2

公开(公告)日：2013-04-23

申请号：US13077569

申请日：2011-03-31

申请人： Bradley P. Smith ,  James W. Miller

发明人： Bradley P. Smith ,  James W. Miller

IPC分类号： H01L21/8238

CPC分类号： H01L29/7881 ,  H01L29/66825

摘要： A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.

摘要翻译： 在晶体管区域和NVM区域的基板上形成第一电介质层，在第一电介质层上形成第一导电层，在第一导电层上形成第二电介质层，在第一导电层上形成第二导电层 第二电介质层。 执行图案化蚀刻以去除晶体管区域中的第二导电层的至少一部分并且暴露第一导电层的延伸部分。 在具有第一图案的晶体管区域上形成第一掩模，其中第一图案是MOSFET的栅极堆叠，以及在延伸部分中从栅极堆叠延伸的延伸部分，以及位于NVM区域上的第二掩模，其具有第二图案 图案，其中所述第二图案是所述NVM单元的栅极堆叠。 然后执行图案化蚀刻。

公开(公告)号：US20120252179A1

公开(公告)日：2012-10-04

申请号：US13077569

申请日：2011-03-31

申请人： Bradley P. Smith ,  James W. Miller

发明人： Bradley P. Smith ,  James W. Miller

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L29/66825

摘要： A first dielectric layer is formed on a substrate in a transistor region and an NVM region, a first conductive layer is formed on the first dielectric layer, a second dielectric layer is formed on the first conductive layer, and a second conductive layer is formed over the second dielectric layer. A patterned etch is performed to remove at least a portion of the second conductive layer in the transistor region and to expose an extension portion of the first conductive layer. A first mask is formed over the transistor region having a first pattern, wherein the first pattern is of a gate stack of the MOSFET and an extension in the extension portion extending from the gate stack, and a second mask over the NVM region having a second pattern, wherein the second pattern is of a gate stack of the NVM cell. A patterned etch is then performed.

摘要翻译： 在晶体管区域和NVM区域的基板上形成第一电介质层，在第一电介质层上形成第一导电层，在第一导电层上形成第二电介质层，在第一导电层上形成第二导电层 第二电介质层。 执行图案化蚀刻以去除晶体管区域中的第二导电层的至少一部分并且暴露第一导电层的延伸部分。 在具有第一图案的晶体管区域上形成第一掩模，其中第一图案是MOSFET的栅极堆叠，并且在从栅极堆叠延伸的延伸部分中的延伸部分以及在NVM区域上的第二掩模，其具有第二图案 图案，其中所述第二图案是所述NVM单元的栅极堆叠。 然后执行图案化蚀刻。

公开(公告)号：US20100129981A1

公开(公告)日：2010-05-27

申请号：US12277455

申请日：2008-11-25

申请人： Bradley P. Smith

发明人： Bradley P. Smith

IPC分类号： H01L21/762

CPC分类号： H01L21/76229

摘要： In one embodiment, a method of forming a via includes providing a semiconductor substrate, wherein the semiconductor substrate comprises a through-via region, forming isolation openings and a sacrificial feature in the through-via region, filling the isolation openings to form isolation regions, forming a dielectric layer over the semiconductor substrate after filling the isolation openings, forming a first portion of a through-via opening in the dielectric layer, forming a second portion of the through-via opening in the semiconductor substrate, wherein forming the second portion of the through-via opening comprises removing the sacrificial feature, and forming a conductive material in the first portion and the second portion of the through-via opening.

摘要翻译： 在一个实施例中，形成通孔的方法包括提供半导体衬底，其中半导体衬底包括通孔区域，在通孔区域中形成隔离开口和牺牲特征，填充隔离开口以形成隔离区域， 在填充所述隔离开口之后，在所述半导体衬底上形成电介质层，在所述电介质层中形成贯通孔的第一部分，形成所述半导体衬底中的所述贯通通孔的第二部分， 通孔通孔包括去除牺牲特征，以及在通孔通孔的第一部分和第二部分中形成导电材料。

公开(公告)号：US06956281B2

公开(公告)日：2005-10-18

申请号：US10224794

申请日：2002-08-21

申请人： Bradley P. Smith ,  Edward O. Travis

发明人： Bradley P. Smith ,  Edward O. Travis

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L2924/0002 ,  Y02P80/30 ,  H01L2924/00

摘要： A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole pairs that separate when created at the PN junction of the border. The photovoltaic current can have a sufficient current density to be destructive to the metal connections to a well if the area of these metal connections to the well is small relative to the length of the border. This photovoltaic current can be reduced below destructive levels by covering the common border sufficiently to reduce the number of photons hitting the common border. The surface area of the connections can also be increased to alleviate the problem.

公开(公告)号：US20150002211A1

公开(公告)日：2015-01-01

申请号：US13929013

申请日：2013-06-27

申请人： Bradley P. Smith ,  Mehul D. Shroff

发明人： Bradley P. Smith ,  Mehul D. Shroff

IPC分类号： H01L29/43 ,  G05F1/10

CPC分类号： H01L21/28176

摘要： A mechanism is provided for extending useable lifetimes of semiconductor devices that are subject to trapped charge carriers in a gate dielectric. Embodiments of the present invention provide heat to the gate dielectric region from one or more sources, where the heat sources are included in a package along with the semiconductor device. It has been determined that heat, when applied during a period when the channel region of a transistor is in accumulation mode or is not providing a current across the channel, can at least partially recover the device from trapped charge carrier effects. Embodiments of the present invention supply heat to the affected gate dielectric region using mechanisms available where the semiconductor device is used (e.g., in the field).

摘要翻译： 提供了一种用于延长在栅极电介质中经受捕获的载流子的半导体器件的可用寿命的机制。 本发明的实施例从一个或多个源向栅介质区提供热量，其中热源与半导体器件一起包括在封装中。 已经确定，当在晶体管的沟道区域处于积聚模式或不通过沟道提供电流的时段期间施加的热量可以至少部分地将器件从俘获的电荷载体效应中恢复。 本发明的实施例使用可用于使用半导体器件的机构（例如，在现场）向受影响的栅极电介质区域供热。

公开(公告)号：US07985655B2

公开(公告)日：2011-07-26

申请号：US12277455

申请日：2008-11-25

申请人： Bradley P. Smith

发明人： Bradley P. Smith

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： In one embodiment, a method of forming a via includes providing a semiconductor substrate, wherein the semiconductor substrate comprises a through-via region, forming isolation openings and a sacrificial feature in the through-via region, filling the isolation openings to form isolation regions, forming a dielectric layer over the semiconductor substrate after filling the isolation openings, forming a first portion of a through-via opening in the dielectric layer, forming a second portion of the through-via opening in the semiconductor substrate, wherein forming the second portion of the through-via opening comprises removing the sacrificial feature, and forming a conductive material in the first portion and the second portion of the through-via opening.

摘要翻译： 在一个实施例中，形成通孔的方法包括提供半导体衬底，其中半导体衬底包括通孔区域，在通孔区域中形成隔离开口和牺牲特征，填充隔离开口以形成隔离区域， 在填充所述隔离开口之后，在所述半导体衬底上形成电介质层，在所述电介质层中形成贯通孔的第一部分，形成所述半导体衬底中的所述贯通通孔的第二部分， 通孔通孔包括去除牺牲特征，以及在通孔通孔的第一部分和第二部分中形成导电材料。

公开(公告)号：US20090020849A1

公开(公告)日：2009-01-22

申请号：US11780900

申请日：2007-07-20

申请人： Bradley P. Smith ,  Edward O. Travis

发明人： Bradley P. Smith ,  Edward O. Travis

IPC分类号： H01L29/00 ,  H01L21/02

CPC分类号： H01L22/20 ,  H01L22/12 ,  H01L28/40

摘要： An electronic device can include electronic components and an insulating layer overlying the electronic components. The electronic device can also include a capacitor overlying the insulating layer, wherein the capacitor includes a first electrode and a second electrode. The second electrode can include an opening, wherein from a top view, a defect lies within the opening. In another aspect, a process of forming an electronic device can include forming a first capacitor electrode layer over a substrate, forming a dielectric layer over the first capacitor electrode layer, and forming a second capacitor electrode layer over the dielectric layer. The process can also include detecting a defect and removing a first portion of the second capacitor electrode layer corresponding to the defect, wherein a second portion of the second capacitor electrode layer remains over the dielectric layer.

摘要翻译： 电子设备可以包括电子部件和覆盖电子部件的绝缘层。 电子器件还可以包括覆盖绝缘层的电容器，其中电容器包括第一电极和第二电极。 第二电极可以包括开口，其中从顶部看，缺陷位于开口内。 另一方面，形成电子器件的方法可以包括在衬底上形成第一电容器电极层，在第一电容器电极层上形成电介质层，并在电介质层上形成第二电容器电极层。 该过程还可以包括检测缺陷并去除对应于缺陷的第二电容器电极层的第一部分，其中第二电容器电极层的第二部分保留在电介质层上。

公开(公告)号：US07353953B2

公开(公告)日：2008-04-08

申请号：US10946477

申请日：2004-09-21

申请人： Davis Freeman, III ,  Robert Novick ,  Bradley P. Smith

发明人： Davis Freeman, III ,  Robert Novick ,  Bradley P. Smith

IPC分类号： B65D69/00 ,  B32B27/12 ,  B65B35/30 ,  G01N1/10 ,  G01N35/02

CPC分类号： G01N35/026 ,  B01L9/06 ,  G01N2035/00277 ,  G01N2035/0465 ,  Y10S206/813 ,  Y10S206/82 ,  Y10S436/809 ,  Y10T436/114165

摘要： Packaged fluid receptacles include: a plurality of fluid receptacles arranged one next to the other to form a composite structure having a top surface, bottom surface and end walls at a first end and a second end and having a longitudinal axis which extends through the end walls; and a removable support which contacts at least the top surface, bottom surface and end walls, the removable support including an attachment for applying a force to remove the support, preferably in a direction along the longitudinal axis. In a preferred embodiment, the support is one-piece and has a single attachment. Preferably, the packaged fluid receptacles are cuvettes usable in a clinical analyzer. A method for inserting a plurality of cuvettes into a clinical analyzer includes: providing packaged cuvettes as described above; inserting the packaged cuvettes into a cuvette loading station of a clinical analyzer in a manner in which the tab remains accessible to application of a force; securing the packaged cuvettes in the loading station; applying a force to the tab to peel back the support from the cuvettes; and removing the support to provide individual cuvettes.

摘要翻译： 封装的流体容器包括：多个彼此相邻布置的流体容器，以形成复合结构，该复合结构在第一端和第二端处具有顶表面，底表面和端壁，并且具有延伸穿过端壁的纵向轴线 ; 以及至少与顶表面，底表面和端壁相接触的可除去的支撑件，所述可除去的支撑件包括用于施加力以移除所述支撑件的附件，优选沿着所述纵向轴线的方向。 在优选实施例中，支撑件是一体的并且具有单个附件。 优选地，包装的流体容器是在临床分析器中可用的比色杯。 将多个比色皿插入临床分析器的方法包括：提供如上所述的包装的比色杯; 将包装的比色杯以临时分析仪的比色皿装载站插入，使得标签仍然可以通过施加力; 将包装的比色杯固定在装载站中; 向所述突片施加力以从所述比色皿剥离所述载体; 并移除支架以提供各自的比色皿。