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公开(公告)号：US20170230011A1
公开(公告)日：2017-08-10
申请号：US15312717
申请日：2015-04-29
Applicant: CommScope Technologies LLC
Inventor： Sammit A. Patel , Yongjie Xu , Qiyun Gu , Richard W. Brown
IPC: H03F1/30 , H03F3/213 , H03F3/193 , H01L23/427 , H01L23/66 , H03F3/21 , H01L25/10 , H05K1/02 , H05K1/18 , H01L23/40 , H01L25/00 , H05K3/34 , H03F3/195 , H01L25/11
CPC classification number: H03F1/301 , H01L23/4006 , H01L23/427 , H01L23/66 , H01L29/7816 , H01L2023/4031 , H01L2023/4062 , H01L2023/4087 , H01L2223/6644 , H01L2924/0002 , H03F3/213 , H03F2200/411 , H03F2200/447 , H03F2200/451 , H05K1/0203 , H05K1/183 , H05K3/3421 , H05K3/3463 , H05K7/2029 , H05K7/20336 , H05K7/20936 , H05K2201/064 , H05K2201/09036 , H05K2201/09063 , H05K2201/10166 , H01L2924/00
Abstract: In one embodiment, an electronic system includes a printed circuit board, one or more packaged semiconductor devices, and a vapor chamber having a top and a bottom and enclosing a sealed cavity that is partially filled with a coolant. The vapor chamber comprises a thermo-conductive and electro-conductive material. The top of the vapor chamber has one or more depressions formed therein, each depression receiving and thermo-conductively connected to at least part of a bottom of a corresponding packaged semiconductor device, which is mounted through a corresponding aperture in the PCB. A heat sink may be thermo-conductively attached to the bottom of the vapor chamber.
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Patent Agency Ranking
公开(公告)号：US10103692B2
公开(公告)日：2018-10-16
申请号：US15312717
申请日：2015-04-29
Applicant: CommScope Technologies LLC
Inventor： Sammit A. Patel , Yongjie Xu , Qiyun Gu , Richard W. Brown
IPC: H03F1/30 , H05K7/20 , H01L23/427 , H05K3/34 , H05K1/18 , H03F3/213 , H01L23/66 , H05K1/02 , H01L23/40 , H01L29/78
Abstract: In one embodiment, an electronic system includes a printed circuit board, one or more packaged semiconductor devices, and a vapor chamber having a top and a bottom and enclosing a sealed cavity that is partially filled with a coolant. The vapor chamber comprises a thermo-conductive and electro-conductive material. The top of the vapor chamber has one or more depressions formed therein, each depression receiving and thermo-conductively connected to at least part of a bottom of a corresponding packaged semiconductor device, which is mounted through a corresponding aperture in the PCB. A heat sink may be thermo-conductively attached to the bottom of the vapor chamber.
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公开(公告)号：US10741920B2
公开(公告)日：2020-08-11
申请号：US16163601
申请日：2018-10-18
Applicant: CommScope Technologies LLC
Inventor： Jonathon C. Veihl , Michael L. Brobston , Richard W. Brown , Charles D. L. Bernardo
Abstract: A stacked patch radiating element includes a dielectric substrate, a ground plane on a first surface of the dielectric substrate, a patch radiator on a second surface of the dielectric substrate, a feed that is configured to connect the patch radiator to a transmission line, a solder layer on the patch radiator opposite the dielectric substrate, and a parasitic radiating element on the solder layer opposite the patch radiator. The parasitic radiating element includes a metal layer on the solder, a parasitic radiator dielectric substrate on the first metal layer opposite the solder, and a parasitic radiator on the parasitic radiator dielectric substrate opposite the first metal layer.
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公开(公告)号：US20190115664A1
公开(公告)日：2019-04-18
申请号：US16163601
申请日：2018-10-18
Applicant: CommScope Technologies LLC
Inventor： Jonathon C. Veihl , Michael L. Brobston , Richard W. Brown , Charles D.L. Bernardo
CPC classification number: H01Q9/0414 , H01Q5/385 , H01Q5/50 , H01Q9/0435 , H01Q21/0087 , H01Q21/065
Abstract: A stacked patch radiating element includes a dielectric substrate, a ground plane on a first surface of the dielectric substrate, a patch radiator on a second surface of the dielectric substrate, a feed that is configured to connect the patch radiator to a transmission line, a solder layer on the patch radiator opposite the dielectric substrate, and a parasitic radiating element on the solder layer opposite the patch radiator. The parasitic radiating element includes a metal layer on the solder, a parasitic radiator dielectric substrate on the first metal layer opposite the solder, and a parasitic radiator on the parasitic radiator dielectric substrate opposite the first metal layer.
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公开(公告)号：US11177572B2
公开(公告)日：2021-11-16
申请号：US16924461
申请日：2020-07-09
Applicant: CommScope Technologies LLC
Inventor： Jonathon C. Veihl , Michael L. Brobston , Richard W. Brown , Charles D. L. Bernardo
Abstract: A stacked patch radiating element includes a dielectric substrate, a ground plane on a first surface of the dielectric substrate, a patch radiator on a second surface of the dielectric substrate, a feed that is configured to connect the patch radiator to a transmission line, a solder layer on the patch radiator opposite the dielectric substrate, and a parasitic radiating element on the solder layer opposite the patch radiator. The parasitic radiating element includes a metal layer on the solder, a parasitic radiator dielectric substrate on the first metal layer opposite the solder, and a parasitic radiator on the parasitic radiator dielectric substrate opposite the first metal layer.
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公开(公告)号：US20200343640A1
公开(公告)日：2020-10-29
申请号：US16924461
申请日：2020-07-09
Applicant: CommScope Technologies LLC
Inventor： Jonathon C. Veihl , Michael L. Brobston , Richard W. Brown , Charles D. L. Bernardo
Abstract: A stacked patch radiating element includes a dielectric substrate, a ground plane on a first surface of the dielectric substrate, a patch radiator on a second surface of the dielectric substrate, a feed that is configured to connect the patch radiator to a transmission line, a solder layer on the patch radiator opposite the dielectric substrate, and a parasitic radiating element on the solder layer opposite the patch radiator. The parasitic radiating element includes a metal layer on the solder, a parasitic radiator dielectric substrate on the first metal layer opposite the solder, and a parasitic radiator on the parasitic radiator dielectric substrate opposite the first metal layer.
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