公开(公告)号：US20130252386A1

公开(公告)日：2013-09-26

申请号：US13892530

申请日：2013-05-13

Applicant: Cree, Inc.

Inventor： Scott T. Sheppard ,  Andrew K. Mackenzie ,  Scott T. Allen ,  Richard P. Smith

IPC: H01L29/66

CPC classification number: H01L29/66431 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/802 ,  H01L2924/13064

Abstract: A III-Nitride field-effect transistor, specifically a HEMT, comprises a channel layer, a barrier layer on the channel layer, an etch stop layer on the cap layer, a dielectric layer on the etch stop layer, a gate recess that extends to the barrier layer, and a gate contact in the gate recess. The etch stop layer may reduce damage associated with forming the recessed gate by not exposing the barrier layer to dry etching. The etch stop layer in the recess is removed and the remaining etch stop layer serves as a passivation layer.

Abstract translation: III型氮化物场效应晶体管，特别是HEMT，包括沟道层，沟道层上的势垒层，覆盖层上的蚀刻停止层，蚀刻停止层上的介电层，延伸到 阻挡层和栅极接触。 蚀刻停止层可以通过不将阻挡层暴露于干蚀刻来减少与形成凹陷栅的相关的损伤。 去除凹槽中的蚀刻停止层，剩余的蚀刻停止层用作钝化层。

公开(公告)号：US09142636B2

公开(公告)日：2015-09-22

申请号：US13892530

申请日：2013-05-13

Applicant: Cree, Inc.

Inventor： Scott T. Sheppard ,  Andrew K. Mackenzie ,  Scott T. Allen ,  Richard P. Smith

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/80 ,  H01L29/43 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/66431 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/802 ,  H01L2924/13064

Abstract: A III-Nitride field-effect transistor, specifically a HEMT, comprises a channel layer, a barrier layer on the channel layer, an etch stop layer on the cap layer, a dielectric layer on the etch stop layer, a gate recess that extends to the barrier layer, and a gate contact in the gate recess. The etch stop layer may reduce damage associated with forming the recessed gate by not exposing the barrier layer to dry etching. The etch stop layer in the recess is removed and the remaining etch stop layer serves as a passivation layer.

Abstract translation: III型氮化物场效应晶体管，特别是HEMT，包括沟道层，沟道层上的势垒层，覆盖层上的蚀刻停止层，蚀刻停止层上的介电层，延伸到 阻挡层和栅极接触。 蚀刻停止层可以通过不将阻挡层暴露于干蚀刻来减少与形成凹陷栅的相关的损伤。 去除凹槽中的蚀刻停止层，剩余的蚀刻停止层用作钝化层。

公开(公告)号：US09224596B2

公开(公告)日：2015-12-29

申请号：US13975491

申请日：2013-08-26

Applicant: Cree, Inc.

Inventor： Adam William Saxler ,  Yifeng Wu ,  Primit Parikh ,  Umesh Mishra ,  Richard Peter Smith ,  Scott T. Sheppard

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/36 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L21/0254 ,  H01L21/0237 ,  H01L21/02425 ,  H01L21/02439 ,  H01L21/02491 ,  H01L21/02581 ,  H01L21/0262 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7787

Abstract: Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive GaN substrate, an insulating or semi-insulating GaN epitaxial layer on the conductive GaN substrate, a GaN based semiconductor device on the GaN epitaxial layer and a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer.

Abstract translation: 提供半导体器件结构和制造半导体器件结构的方法，其包括在导电半导体衬底和/或导电层上的半绝缘或绝缘GaN外延层。 半绝缘或绝缘的GaN外延层具有至少约4μm的厚度。 还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括在导电SiC衬底上的导电SiC衬底和绝缘或半绝缘GaN外延层。 GaN外延层具有至少约4μm的厚度。 还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括导电GaN衬底，导电GaN衬底上的绝缘或半绝缘GaN外延层，GaN外延层上的GaN基半导体器件和 通孔和通孔中相应的通孔金属延伸穿过GaN基半导体器件和GaN外延层的层。

公开(公告)号：US09984881B2

公开(公告)日：2018-05-29

申请号：US14332575

申请日：2014-07-16

Applicant: Cree, Inc.

Inventor： Scott T. Sheppard ,  Alexander V. Suvorov

IPC: H01L21/338 ,  H01L21/265 ,  H01L29/812 ,  H01L29/80 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L21/2654 ,  H01L21/26553 ,  H01L29/66212 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/802 ,  H01L29/812

Abstract: Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer. A first electrode is formed on the implanted region of the second semiconductor layer, and a second electrode is formed on a non-implanted region of the second semiconductor layer. Related devices are also discussed.

公开(公告)号：US20140329367A1

公开(公告)日：2014-11-06

申请号：US14332575

申请日：2014-07-16

Applicant: Cree, Inc.

Inventor： Scott T. Sheppard ,  Alexander V. Suvorov

IPC: H01L21/265 ,  H01L29/66

CPC classification number: H01L21/2654 ,  H01L21/26553 ,  H01L29/66212 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/802 ,  H01L29/812

Abstract: Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer. A first electrode is formed on the implanted region of the second semiconductor layer, and a second electrode is formed on a non-implanted region of the second semiconductor layer. Related devices are also discussed.

Abstract translation: 制造半导体器件的方法包括形成第一导电类型的第一半导体层并具有第一掺杂剂浓度，以及在第一半导体层上形成第二半导体层。 第二半导体层具有小于第一掺杂剂浓度的第二掺杂剂浓度。 将离子注入到第二半导体层中以形成延伸穿过第二半导体层的与第一半导体层接触的第一导电类型的注入区。 第一电极形成在第二半导体层的注入区上，第二电极形成在第二半导体层的非注入区上。 还讨论了相关设备。

公开(公告)号：US20130344687A1

公开(公告)日：2013-12-26

申请号：US13975491

申请日：2013-08-26

Applicant: Cree, Inc.

Inventor： Adam William Saxler ,  Yifeng Wu ,  Primit Parikh ,  Umesh Mishra ,  Richard Peter Smith ,  Scott T. Sheppard

IPC: H01L21/02

CPC classification number: H01L21/0254 ,  H01L21/0237 ,  H01L21/02425 ,  H01L21/02439 ,  H01L21/02491 ,  H01L21/02581 ,  H01L21/0262 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7787

Abstract: Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive GaN substrate, an insulating or semi-insulating GaN epitaxial layer on the conductive GaN substrate, a GaN based semiconductor device on the GaN epitaxial layer and a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer.

Abstract translation: 提供半导体器件结构和制造半导体器件结构的方法，其包括在导电半导体衬底和/或导电层上的半绝缘或绝缘GaN外延层。 半绝缘或绝缘GaN外延层具有至少约4μm的厚度。 还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括在导电SiC衬底上的导电SiC衬底和绝缘或半绝缘GaN外延层。 GaN外延层具有至少约4μm的厚度。 还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括导电GaN衬底，导电GaN衬底上的绝缘或半绝缘GaN外延层，GaN外延层上的GaN基半导体器件和 通孔和通孔中相应的通孔金属延伸穿过GaN基半导体器件和GaN外延层的层。