公开(公告)号：US10020317B2

公开(公告)日：2018-07-10

申请号：US15078156

申请日：2016-03-23

Applicant: Cypress Semiconductor Corporation

Inventor： Renhua Zhang ,  Lei Xue ,  Rinji Sugino ,  Krishnaswamy Ramkumar

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/161 ,  H01L29/10 ,  H01L29/04 ,  H01L29/167 ,  H01L21/02 ,  H01L23/528 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/167 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518

Abstract: A 3-D/vertical non-volatile (NV) memory device such as 3-D NAND flash memory and fabrication method thereof, the NV memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes polycrystalline germanium or silicon-germanium.

公开(公告)号：US10256137B2

公开(公告)日：2019-04-09

申请号：US15802721

申请日：2017-11-03

Applicant: Cypress Semiconductor Corporation

Inventor： Ching-Huang Lu ,  Lei Xue ,  Kenichi Ohtsuka ,  Simon Siu-Sing Chan ,  Rinji Sugino

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11521 ,  H01L27/11568

Abstract: An A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

公开(公告)号：US20190043751A1

公开(公告)日：2019-02-07

申请号：US16154907

申请日：2018-10-09

Applicant: Cypress Semiconductor Corporation

Inventor： Rinji Sugino ,  Fei Wang

IPC: H01L21/764

Abstract: A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.

公开(公告)号：US11430689B2

公开(公告)日：2022-08-30

申请号：US16154907

申请日：2018-10-09

Applicant: Cypress Semiconductor Corporation

Inventor： Rinji Sugino ,  Fei Wang

IPC: H01L21/764

Abstract: A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.

公开(公告)号：US20190198611A1

公开(公告)日：2019-06-27

申请号：US16226389

申请日：2018-12-19

Applicant: Cypress Semiconductor Corporation

Inventor： Rinji Sugino ,  Lei Xue ,  Ching-Huang LU ,  Simon S. Chan

IPC: H01L29/06 ,  H01L29/161 ,  H01L21/324 ,  H01L21/764 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/3247 ,  H01L21/76224 ,  H01L21/764 ,  H01L29/0684 ,  H01L29/161

Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.

公开(公告)号：US20180323208A1

公开(公告)日：2018-11-08

申请号：US16020546

申请日：2018-06-27

Applicant: Cypress Semiconductor Corporation

Inventor： Rinji Sugino ,  Scott A. Bell ,  Lei Xue

IPC: H01L27/11582 ,  H01L27/11565 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11565 ,  H01L27/1157

Abstract: A method of forming a vertical non-volatile (NV) memory device such as 3-D NAND flash memory includes forming a vertical NV memory cell string within an opening disposed in a stack of alternating layers of a first layer and a second layer over a substrate, and dividing the vertical NV memory cell string into two halves with a first vertical deep trench and an isolation dielectric pillar formed in the first vertical deep trench, such that memory bit density of the divided vertical NV memory cell strings double the memory bits of the device.

公开(公告)号：US20180166323A1

公开(公告)日：2018-06-14

申请号：US15802721

申请日：2017-11-03

Applicant: Cypress Semiconductor Corporation

Inventor： Ching-Huang LU ,  Lei Xue ,  Kenichi Ohtsuka ,  Simon Siu-Sing Chan ,  Rinji Sugino

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L21/76237 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823481 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/66484 ,  H01L29/66537 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the buried trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

公开(公告)号：US20160211321A1

公开(公告)日：2016-07-21

申请号：US15012644

申请日：2016-02-01

Applicant: Cypress Semiconductor Corporation

Inventor： Rinji Sugino ,  Lei Xue ,  Ching-Huang LU ,  Simon Siu-Sing CHAN

IPC: H01L29/06 ,  H01L29/161

CPC classification number: H01L29/0649 ,  H01L21/3247 ,  H01L21/76224 ,  H01L21/764 ,  H01L29/0684 ,  H01L29/161

Abstract: A system for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) is disclosed herein. An integrated circuit (IC) comprises a substrate, a first device, a second device, and an isolator. The isolator is positioned between first and second device. The isolator comprises one or more cavities. The isolator may be filled with dielectric material.

Abstract translation: 本文公开了一种用于在高密度集成电路（IC）中的紧密间隔的器件之间提供电隔离的系统。 集成电路（IC）包括衬底，第一器件，第二器件和隔离器。 隔离器位于第一和第二装置之间。 隔离器包括一个或多个空腔。 隔离器可以填充介电材料。

公开(公告)号：US09831114B1

公开(公告)日：2017-11-28

申请号：US15191882

申请日：2016-06-24

Applicant: Cypress Semiconductor Corporation

Inventor： Ching-Huang Lu ,  Lei Xue ,  Kenichi Ohtsuka ,  Rinji Sugino ,  Simon Siu-Sing Chan

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/76237 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823481 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/66484 ,  H01L29/66537 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

公开(公告)号：US20170263623A1

公开(公告)日：2017-09-14

申请号：US15078156

申请日：2016-03-23

Applicant: Cypress Semiconductor Corporation

Inventor： Renhua Zhang ,  Lei Xue ,  Rinji Sugino ,  Krishnaswamy Ramkumar

IPC: H01L27/11582 ,  H01L29/161 ,  H01L29/10 ,  H01L29/04 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L21/28 ,  H01L21/311 ,  H01L29/51 ,  H01L29/167

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/167 ,  H01L29/513 ,  H01L29/518

Abstract: A 3-D/vertical non-volatile (NV) memory device such as 3-D NAND flash memory and fabrication method thereof, the NV memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes polycrystalline germanium or silicon-germanium.