公开(公告)号：US20200152851A1

公开(公告)日：2020-05-14

申请号：US16681431

申请日：2019-11-12

Applicant: D-WAVE SYSTEMS INC.

Inventor： Trevor M. Lanting ,  Danica W. Marsden ,  Byong Hyop Oh ,  Eric G. Ladizinsky ,  Shuiyuan Huang ,  J. Jason Yao ,  Douglas P. Stadtler

IPC: H01L39/02 ,  G06N10/00 ,  H01L39/24 ,  H01L39/22

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

公开(公告)号：US11856871B2

公开(公告)日：2023-12-26

申请号：US17681303

申请日：2022-02-25

Applicant: D-WAVE SYSTEMS INC.

Inventor： Trevor M. Lanting ,  Danica W. Marsden ,  Byong Hyop Oh ,  Eric G. Ladizinsky ,  Shuiyuan Huang ,  J. Jason Yao ,  Douglas P. Stadtler

IPC: H01L39/02 ,  H10N60/80 ,  G06N10/00 ,  H10N60/12 ,  H10N60/01 ,  H10N69/00

CPC classification number: H10N60/805 ,  G06N10/00 ,  H10N60/0156 ,  H10N60/0912 ,  H10N60/12 ,  H10N69/00

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

公开(公告)号：US20180219150A1

公开(公告)日：2018-08-02

申请号：US15503367

申请日：2015-08-12

Applicant: D-Wave Systems Inc.

Inventor： Trevor Michael Lanting ,  Eric G. Ladizinsky ,  J. Jason Yao ,  Byong Hyop Oh

IPC: H01L39/24 ,  H01L39/22 ,  H01L21/768

CPC classification number: H01L39/2493 ,  H01L21/76891 ,  H01L23/53285 ,  H01L27/18 ,  H01L39/223

Abstract: Fabricating wiring layers above a Josephson junction multi-layer may include removing a part of the multilayer; depositing an insulating layer to overlie a part of the multilayer; and patterning the insulating layer to define a hole in the insulating layer. The method includes depositing a first superconducting wiring layer over a part of the insulating layer and within a portion of the hole. Further, insulating and wiring layers may be deposited and a topmost wiring layer defined. The method includes depositing a passivating layer to overlie the topmost wiring layer. Fabricating a superconducting integrated circuit comprising a hybrid dielectric system may include depositing a high-quality dielectric layer that overlies a superconducting feature. The method includes depositing a second dielectric layer that overlies at least part of the high-quality dielectric layer. The second dielectric layer can comprise a conventional dielectric material.

公开(公告)号：US20230240154A1

公开(公告)日：2023-07-27

申请号：US18010283

申请日：2021-06-22

Applicant: D-WAVE SYSTEMS INC.

Inventor： Byong Hyop Oh ,  Eric G. Ladizinsky ,  J. Jason Yao

IPC: H10N60/01 ,  H10N60/80

CPC classification number: H10N60/01 ,  H10N60/80

Abstract: Methods of forming superconducting integrated circuits are discussed. The method includes depositing a first superconducting metal layer to overlie at least a portion of a substrate, depositing a dielectric layer to cover a first region of the first superconducting metal layer, pattering the dielectric layer to expose at least a portion of the first region of the first superconducting metal layer and form an opening, and depositing a second superconducting metal layer at an ambient temperature that is less than a melting temperature of the second superconducting metal layer such that the second superconducting metal layer fills the opening and conductively contacts the at least a portion of the first region of the first superconducting metal layer.

公开(公告)号：US20220263007A1

公开(公告)日：2022-08-18

申请号：US17681303

申请日：2022-02-25

Applicant: D-WAVE SYSTEMS INC.

Inventor： Trevor M. Lanting ,  Danica W. Marsden ,  Byong Hyop Oh ,  Eric G. Ladizinsky ,  Shuiyuan Huang ,  J. Jason Yao ,  Douglas P. Stadtler

IPC: H01L39/02 ,  G06N10/00 ,  H01L39/22 ,  H01L39/24

Abstract: Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

公开(公告)号：US10454015B2

公开(公告)日：2019-10-22

申请号：US15503367

申请日：2015-08-12

Applicant: D-Wave Systems Inc.

Inventor： Trevor Michael Lanting ,  Eric G. Ladizinsky ,  J. Jason Yao ,  Byong Hyop Oh

IPC: H01L39/24 ,  H01L27/18 ,  H01L39/22 ,  H01L21/768 ,  H01L23/532

Abstract: Fabricating wiring layers above a Josephson junction multi-layer may include removing a part of the multilayer; depositing an insulating layer to overlie a part of the multilayer; and patterning the insulating layer to define a hole in the insulating layer. The method includes depositing a first superconducting wiring layer over a part of the insulating layer and within a portion of the hole. Further, insulating and wiring layers may be deposited and a topmost wiring layer defined. The method includes depositing a passivating layer to overlie the topmost wiring layer. Fabricating a superconducting integrated circuit comprising a hybrid dielectric system may include depositing a high-quality dielectric layer that overlies a superconducting feature. The method includes depositing a second dielectric layer that overlies at least part of the high-quality dielectric layer. The second dielectric layer can comprise a conventional dielectric material.